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Merge tag 'cris-for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper...
[cascardo/linux.git]
/
arch
/
arm
/
kernel
/
setup.c
diff --git
a/arch/arm/kernel/setup.c
b/arch/arm/kernel/setup.c
index
df7f2a7
..
34e3f3c
100644
(file)
--- a/
arch/arm/kernel/setup.c
+++ b/
arch/arm/kernel/setup.c
@@
-114,19
+114,19
@@
EXPORT_SYMBOL(elf_hwcap2);
#ifdef MULTI_CPU
#ifdef MULTI_CPU
-struct processor processor __r
ead_mostly
;
+struct processor processor __r
o_after_init
;
#endif
#ifdef MULTI_TLB
#endif
#ifdef MULTI_TLB
-struct cpu_tlb_fns cpu_tlb __r
ead_mostly
;
+struct cpu_tlb_fns cpu_tlb __r
o_after_init
;
#endif
#ifdef MULTI_USER
#endif
#ifdef MULTI_USER
-struct cpu_user_fns cpu_user __r
ead_mostly
;
+struct cpu_user_fns cpu_user __r
o_after_init
;
#endif
#ifdef MULTI_CACHE
#endif
#ifdef MULTI_CACHE
-struct cpu_cache_fns cpu_cache __r
ead_mostly
;
+struct cpu_cache_fns cpu_cache __r
o_after_init
;
#endif
#ifdef CONFIG_OUTER_CACHE
#endif
#ifdef CONFIG_OUTER_CACHE
-struct outer_cache_fns outer_cache __r
ead_mostly
;
+struct outer_cache_fns outer_cache __r
o_after_init
;
EXPORT_SYMBOL(outer_cache);
#endif
EXPORT_SYMBOL(outer_cache);
#endif
@@
-290,12
+290,9
@@
static int cpu_has_aliasing_icache(unsigned int arch)
/* arch specifies the register format */
switch (arch) {
case CPU_ARCH_ARMv7:
/* arch specifies the register format */
switch (arch) {
case CPU_ARCH_ARMv7:
- asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
- : /* No output operands */
- : "r" (1));
+ set_csselr(CSSELR_ICACHE | CSSELR_L1);
isb();
isb();
- asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
- : "=r" (id_reg));
+ id_reg = read_ccsidr();
line_size = 4 << ((id_reg & 0x7) + 2);
num_sets = ((id_reg >> 13) & 0x7fff) + 1;
aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
line_size = 4 << ((id_reg & 0x7) + 2);
num_sets = ((id_reg >> 13) & 0x7fff) + 1;
aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
@@
-315,11
+312,12
@@
static void __init cacheid_init(void)
{
unsigned int arch = cpu_architecture();
{
unsigned int arch = cpu_architecture();
- if (arch == CPU_ARCH_ARMv7M) {
- cacheid = 0;
- } else if (arch >= CPU_ARCH_ARMv6) {
+ if (arch >= CPU_ARCH_ARMv6) {
unsigned int cachetype = read_cpuid_cachetype();
unsigned int cachetype = read_cpuid_cachetype();
- if ((cachetype & (7 << 29)) == 4 << 29) {
+
+ if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {
+ cacheid = 0;
+ } else if ((cachetype & (7 << 29)) == 4 << 29) {
/* ARMv7 register format */
arch = CPU_ARCH_ARMv7;
cacheid = CACHEID_VIPT_NONALIASING;
/* ARMv7 register format */
arch = CPU_ARCH_ARMv7;
cacheid = CACHEID_VIPT_NONALIASING;