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ARM: imx: irq: fix buggy usage of irq_data irq field
[cascardo/linux.git]
/
arch
/
arm
/
mach-imx
/
gpc.c
diff --git
a/arch/arm/mach-imx/gpc.c
b/arch/arm/mach-imx/gpc.c
index
82ea74e
..
1455829
100644
(file)
--- a/
arch/arm/mach-imx/gpc.c
+++ b/
arch/arm/mach-imx/gpc.c
@@
-56,14
+56,14
@@
void imx_gpc_post_resume(void)
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
- unsigned int idx = d->irq / 32 - 1;
+ unsigned int idx = d->
hw
irq / 32 - 1;
u32 mask;
/* Sanity check for SPI irq */
u32 mask;
/* Sanity check for SPI irq */
- if (d->irq < 32)
+ if (d->
hw
irq < 32)
return -EINVAL;
return -EINVAL;
- mask = 1 << d->irq % 32;
+ mask = 1 << d->
hw
irq % 32;
gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
gpc_wake_irqs[idx] & ~mask;
gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
gpc_wake_irqs[idx] & ~mask;
@@
-97,12
+97,12
@@
void imx_gpc_irq_unmask(struct irq_data *d)
u32 val;
/* Sanity check for SPI irq */
u32 val;
/* Sanity check for SPI irq */
- if (d->irq < 32)
+ if (d->
hw
irq < 32)
return;
return;
- reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+ reg = gpc_base + GPC_IMR1 + (d->
hw
irq / 32 - 1) * 4;
val = readl_relaxed(reg);
val = readl_relaxed(reg);
- val &= ~(1 << d->irq % 32);
+ val &= ~(1 << d->
hw
irq % 32);
writel_relaxed(val, reg);
}
writel_relaxed(val, reg);
}
@@
-112,12
+112,12
@@
void imx_gpc_irq_mask(struct irq_data *d)
u32 val;
/* Sanity check for SPI irq */
u32 val;
/* Sanity check for SPI irq */
- if (d->irq < 32)
+ if (d->
hw
irq < 32)
return;
return;
- reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+ reg = gpc_base + GPC_IMR1 + (d->
hw
irq / 32 - 1) * 4;
val = readl_relaxed(reg);
val = readl_relaxed(reg);
- val |= 1 << (d->irq % 32);
+ val |= 1 << (d->
hw
irq % 32);
writel_relaxed(val, reg);
}
writel_relaxed(val, reg);
}