Merge branch 'work.splice_read' of git://git.kernel.org/pub/scm/linux/kernel/git...

[cascardo/linux.git] / arch / arm / mm / cache-l2x0.c

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index cc12905..d1870c7 100644 (file)
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -142,6 +142,8 @@ static void l2c_disable(void)
 {
        void __iomem *base = l2x0_base;
 
+       l2x0_pmu_suspend();
+
        outer_cache.flush_all();
        l2c_write_sec(0, base, L2X0_CTRL);
        dsb(st);
@@ -159,6 +161,8 @@ static void l2c_resume(void)
        /* Do not touch the controller if already enabled. */
        if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
                l2c_enable(base, l2x0_data->num_lock);
+
+       l2x0_pmu_resume();
 }
 
 /*
@@ -709,9 +713,8 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
        if (revision >= L310_CACHE_ID_RTL_R3P0 &&
            revision < L310_CACHE_ID_RTL_R3P2) {
                u32 val = l2x0_saved_regs.prefetch_ctrl;
-               /* I don't think bit23 is required here... but iMX6 does so */
-               if (val & (BIT(30) | BIT(23))) {
-                       val &= ~(BIT(30) | BIT(23));
+               if (val & L310_PREFETCH_CTRL_DBL_LINEFILL) {
+                       val &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
                        l2x0_saved_regs.prefetch_ctrl = val;
                        errata[n++] = "752271";
                }
@@ -892,6 +895,8 @@ static int __init __l2c_init(const struct l2c_init_data *data,
        pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
                data->type, cache_id, aux);
 
+       l2x0_pmu_register(l2x0_base, cache_id);
+
        return 0;
 }