Merge tag 'cris-for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper...
[cascardo/linux.git] / arch / arm64 / boot / dts / hisilicon / hi6220.dtsi
index 4f27041..17839db 100644 (file)
                        #clock-cells = <1>;
                };
 
+               medianoc_ade: medianoc_ade@f4520000 {
+                       compatible = "syscon";
+                       reg = <0x0 0xf4520000 0x0 0x4000>;
+               };
+
                stub_clock: stub_clock {
                        compatible = "hisilicon,hi6220-stub-clk";
                        hisilicon,hi6220-clk-sram = <&sram>;
                        interrupts = <0x0 0x48 0x4>;
                        clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
                        clock-names = "ciu", "biu";
+                       resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
                        bus-width = <0x8>;
                        vmmc-supply = <&ldo19>;
                        pinctrl-names = "default";
                        card-detect-delay = <200>;
                        hisilicon,peripheral-syscon = <&ao_ctrl>;
                        cap-sd-highspeed;
+                       sd-uhs-sdr12;
+                       sd-uhs-sdr25;
+                       sd-uhs-sdr50;
                        reg = <0x0 0xf723e000 0x0 0x1000>;
                        interrupts = <0x0 0x49 0x4>;
                        #address-cells = <0x1>;
                        #size-cells = <0x0>;
                        clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
                        clock-names = "ciu", "biu";
+                       resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
                        vqmmc-supply = <&ldo7>;
                        vmmc-supply = <&ldo10>;
                        bus-width = <0x4>;
                        interrupts = <0x0 0x4a 0x4>;
                        clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
                        clock-names = "ciu", "biu";
+                       resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
                        bus-width = <0x4>;
                        broken-cd;
                        pinctrl-names = "default", "idle";
                                };
                        };
                };
+
+               ade: ade@f4100000 {
+                       compatible = "hisilicon,hi6220-ade";
+                       reg = <0x0 0xf4100000 0x0 0x7800>;
+                       reg-names = "ade_base";
+                       hisilicon,noc-syscon = <&medianoc_ade>;
+                       resets = <&media_ctrl MEDIA_ADE>;
+                       interrupts = <0 115 4>; /* ldi interrupt */
+
+                       clocks = <&media_ctrl HI6220_ADE_CORE>,
+                                <&media_ctrl HI6220_CODEC_JPEG>,
+                                <&media_ctrl HI6220_ADE_PIX_SRC>;
+                       /*clock name*/
+                       clock-names  = "clk_ade_core",
+                                      "clk_codec_jpeg",
+                                      "clk_ade_pix";
+
+                       assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
+                               <&media_ctrl HI6220_CODEC_JPEG>;
+                       assigned-clock-rates = <360000000>, <288000000>;
+                       dma-coherent;
+                       status = "disabled";
+
+                       port {
+                               ade_out: endpoint {
+                                       remote-endpoint = <&dsi_in>;
+                               };
+                       };
+               };
+
+               dsi: dsi@f4107800 {
+                       compatible = "hisilicon,hi6220-dsi";
+                       reg = <0x0 0xf4107800 0x0 0x100>;
+                       clocks = <&media_ctrl  HI6220_DSI_PCLK>;
+                       clock-names = "pclk";
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               /* 0 for input port */
+                               port@0 {
+                                       reg = <0>;
+                                       dsi_in: endpoint {
+                                               remote-endpoint = <&ade_out>;
+                                       };
+                               };
+                       };
+               };
        };
 };