arm64: KVM: Move most of the fault decoding to C

[cascardo/linux.git] / arch / arm64 / kvm / hyp / switch.c

diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 731f0a2..ecf5b05 100644 (file)
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -15,6 +15,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/types.h>
 #include <asm/kvm_asm.h>
 
 #include "hyp.h"
@@ -149,6 +150,86 @@ static void __hyp_text __vgic_restore_state(struct kvm_vcpu *vcpu)
        __vgic_call_restore_state()(vcpu);
 }
 
+static bool __hyp_text __true_value(void)
+{
+       return true;
+}
+
+static bool __hyp_text __false_value(void)
+{
+       return false;
+}
+
+static hyp_alternate_select(__check_arm_834220,
+                           __false_value, __true_value,
+                           ARM64_WORKAROUND_834220);
+
+static bool __hyp_text __translate_far_to_hpfar(u64 far, u64 *hpfar)
+{
+       u64 par, tmp;
+
+       /*
+        * Resolve the IPA the hard way using the guest VA.
+        *
+        * Stage-1 translation already validated the memory access
+        * rights. As such, we can use the EL1 translation regime, and
+        * don't have to distinguish between EL0 and EL1 access.
+        *
+        * We do need to save/restore PAR_EL1 though, as we haven't
+        * saved the guest context yet, and we may return early...
+        */
+       par = read_sysreg(par_el1);
+       asm volatile("at s1e1r, %0" : : "r" (far));
+       isb();
+
+       tmp = read_sysreg(par_el1);
+       write_sysreg(par, par_el1);
+
+       if (unlikely(tmp & 1))
+               return false; /* Translation failed, back to guest */
+
+       /* Convert PAR to HPFAR format */
+       *hpfar = ((tmp >> 12) & ((1UL << 36) - 1)) << 4;
+       return true;
+}
+
+static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
+{
+       u64 esr = read_sysreg_el2(esr);
+       u8 ec = esr >> ESR_ELx_EC_SHIFT;
+       u64 hpfar, far;
+
+       vcpu->arch.fault.esr_el2 = esr;
+
+       if (ec != ESR_ELx_EC_DABT_LOW && ec != ESR_ELx_EC_IABT_LOW)
+               return true;
+
+       far = read_sysreg_el2(far);
+
+       /*
+        * The HPFAR can be invalid if the stage 2 fault did not
+        * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
+        * bit is clear) and one of the two following cases are true:
+        *   1. The fault was due to a permission fault
+        *   2. The processor carries errata 834220
+        *
+        * Therefore, for all non S1PTW faults where we either have a
+        * permission fault or the errata workaround is enabled, we
+        * resolve the IPA using the AT instruction.
+        */
+       if (!(esr & ESR_ELx_S1PTW) &&
+           (__check_arm_834220()() || (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {
+               if (!__translate_far_to_hpfar(far, &hpfar))
+                       return false;
+       } else {
+               hpfar = read_sysreg(hpfar_el2);
+       }
+
+       vcpu->arch.fault.far_el2 = far;
+       vcpu->arch.fault.hpfar_el2 = hpfar;
+       return true;
+}
+
 static int __hyp_text __guest_run(struct kvm_vcpu *vcpu)
 {
        struct kvm_cpu_context *host_ctxt;
@@ -180,9 +261,13 @@ static int __hyp_text __guest_run(struct kvm_vcpu *vcpu)
        __debug_restore_state(vcpu, kern_hyp_va(vcpu->arch.debug_ptr), guest_ctxt);
 
        /* Jump in the fire! */
+again:
        exit_code = __guest_enter(vcpu, host_ctxt);
        /* And we're baaack! */
 
+       if (exit_code == ARM_EXCEPTION_TRAP && !__populate_fault_info(vcpu))
+               goto again;
+
        fp_enabled = __fpsimd_enabled();
 
        __sysreg_save_guest_state(guest_ctxt);