Merge tag 'iwlwifi-next-for-kalle-2014-12-30' of https://git.kernel.org/pub/scm/linux...

[cascardo/linux.git] / arch / mips / include / asm / pgtable-32.h

diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index cd7d606..68984b6 100644 (file)
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -69,7 +69,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
 # define VMALLOC_END   (FIXADDR_START-2*PAGE_SIZE)
 #endif
 
-#ifdef CONFIG_64BIT_PHYS_ADDR
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
 #define pte_ERROR(e) \
        printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
 #else
@@ -103,7 +103,7 @@ static inline void pmd_clear(pmd_t *pmdp)
        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
 }
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
 #define pte_page(x)            pfn_to_page(pte_pfn(x))
 #define pte_pfn(x)             ((unsigned long)((x).pte_high >> 6))
 static inline pte_t
@@ -126,7 +126,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #define pte_pfn(x)             ((unsigned long)((x).pte >> _PFN_SHIFT))
 #define pfn_pte(pfn, prot)     __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
 #endif
-#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
+#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
 
 #define __pgd_offset(address)  pgd_index(address)
 #define __pud_offset(address)  (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
@@ -155,73 +155,75 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 
 /* Swap entries must have VALID bit cleared. */
-#define __swp_type(x)          (((x).val >> 10) & 0x1f)
-#define __swp_offset(x)                ((x).val >> 15)
-#define __swp_entry(type,offset)       \
-       ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
+#define __swp_type(x)                  (((x).val >> 10) & 0x1f)
+#define __swp_offset(x)                        ((x).val >> 15)
+#define __swp_entry(type,offset)       ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
+#define __pte_to_swp_entry(pte)                ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)          ((pte_t) { (x).val })
 
 /*
- * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
+ * Encode and decode a nonlinear file mapping entry
  */
-#define PTE_FILE_MAX_BITS      28
-
-#define pte_to_pgoff(_pte)     ((((_pte).pte >> 1 ) & 0x07) | \
-                                (((_pte).pte >> 2 ) & 0x38) | \
-                                (((_pte).pte >> 10) <<  6 ))
+#define pte_to_pgoff(_pte)             ((((_pte).pte >> 1 ) & 0x07) | \
+                                        (((_pte).pte >> 2 ) & 0x38) | \
+                                        (((_pte).pte >> 10) <<  6 ))
 
-#define pgoff_to_pte(off)      ((pte_t) { (((off) & 0x07) << 1 ) | \
-                                          (((off) & 0x38) << 2 ) | \
-                                          (((off) >>  6 ) << 10) | \
-                                          _PAGE_FILE })
+#define pgoff_to_pte(off)              ((pte_t) { (((off) & 0x07) << 1 ) | \
+                                                  (((off) & 0x38) << 2 ) | \
+                                                  (((off) >>  6 ) << 10) | \
+                                                  _PAGE_FILE })
 
+/*
+ * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
+ */
+#define PTE_FILE_MAX_BITS              28
 #else
 
+#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+
 /* Swap entries must have VALID and GLOBAL bits cleared. */
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-#define __swp_type(x)          (((x).val >> 2) & 0x1f)
-#define __swp_offset(x)                 ((x).val >> 7)
-#define __swp_entry(type,offset)       \
-               ((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
-#else
-#define __swp_type(x)          (((x).val >> 8) & 0x1f)
-#define __swp_offset(x)                 ((x).val >> 13)
-#define __swp_entry(type,offset)       \
-               ((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
-#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
+#define __swp_type(x)                  (((x).val >> 2) & 0x1f)
+#define __swp_offset(x)                         ((x).val >> 7)
+#define __swp_entry(type,offset)       ((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
+#define __pte_to_swp_entry(pte)                ((swp_entry_t) { (pte).pte_high })
+#define __swp_entry_to_pte(x)          ((pte_t) { 0, (x).val })
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 /*
  * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
  */
-#define PTE_FILE_MAX_BITS      30
-
-#define pte_to_pgoff(_pte)     ((_pte).pte_high >> 2)
-#define pgoff_to_pte(off)      ((pte_t) { _PAGE_FILE, (off) << 2 })
+#define pte_to_pgoff(_pte)             ((_pte).pte_high >> 2)
+#define pgoff_to_pte(off)              ((pte_t) { _PAGE_FILE, (off) << 2 })
 
+#define PTE_FILE_MAX_BITS              30
 #else
 /*
- * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
+ * Constraints:
+ *      _PAGE_PRESENT at bit 0
+ *      _PAGE_MODIFIED at bit 4
+ *      _PAGE_GLOBAL at bit 6
+ *      _PAGE_VALID at bit 7
  */
-#define PTE_FILE_MAX_BITS      28
+#define __swp_type(x)                  (((x).val >> 8) & 0x1f)
+#define __swp_offset(x)                         ((x).val >> 13)
+#define __swp_entry(type,offset)       ((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
+#define __pte_to_swp_entry(pte)                ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)          ((pte_t) { (x).val })
 
-#define pte_to_pgoff(_pte)     ((((_pte).pte >> 1) & 0x7) | \
-                                (((_pte).pte >> 2) & 0x8) | \
-                                (((_pte).pte >> 8) <<  4))
+/*
+ * Encode and decode a nonlinear file mapping entry
+ */
+#define pte_to_pgoff(_pte)             ((((_pte).pte >> 1) & 0x7) | \
+                                        (((_pte).pte >> 2) & 0x8) | \
+                                        (((_pte).pte >> 8) <<  4))
 
-#define pgoff_to_pte(off)      ((pte_t) { (((off) & 0x7) << 1) | \
-                                          (((off) & 0x8) << 2) | \
-                                          (((off) >>  4) << 8) | \
-                                          _PAGE_FILE })
-#endif
+#define pgoff_to_pte(off)              ((pte_t) { (((off) & 0x7) << 1) | \
+                                                  (((off) & 0x8) << 2) | \
+                                                  (((off) >>  4) << 8) | \
+                                                  _PAGE_FILE })
 
-#endif
+#define PTE_FILE_MAX_BITS              28
+#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
-#define __swp_entry_to_pte(x)  ((pte_t) { 0, (x).val })
-#else
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x)  ((pte_t) { (x).val })
-#endif
+#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */
 
 #endif /* _ASM_PGTABLE_32_H */