MIPS: Loongson 3: Add IRQ init and dispatch support

[cascardo/linux.git] / arch / mips / loongson / loongson-3 / irq.c

diff --git a/arch/mips/loongson/loongson-3/irq.c b/arch/mips/loongson/loongson-3/irq.c
new file mode 100644 (file)
index 0000000..b2dc62b
--- /dev/null
+++ b/arch/mips/loongson/loongson-3/irq.c
@@ -0,0 +1,96 @@
+#include <loongson.h>
+#include <irq.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+
+unsigned int ht_irq[] = {1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
+
+static void ht_irqdispatch(void)
+{
+       unsigned int i, irq;
+
+       irq = LOONGSON_HT1_INT_VECTOR(0);
+       LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
+
+       for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
+               if (irq & (0x1 << ht_irq[i]))
+                       do_IRQ(ht_irq[i]);
+       }
+}
+
+void mach_irq_dispatch(unsigned int pending)
+{
+       if (pending & CAUSEF_IP7)
+               do_IRQ(LOONGSON_TIMER_IRQ);
+       else if (pending & CAUSEF_IP3)
+               ht_irqdispatch();
+       else if (pending & CAUSEF_IP2)
+               do_IRQ(LOONGSON_UART_IRQ);
+       else {
+               pr_err("%s : spurious interrupt\n", __func__);
+               spurious_interrupt();
+       }
+}
+
+static struct irqaction cascade_irqaction = {
+       .handler = no_action,
+       .name = "cascade",
+};
+
+static inline void mask_loongson_irq(struct irq_data *d)
+{
+       clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+       irq_disable_hazard();
+}
+
+static inline void unmask_loongson_irq(struct irq_data *d)
+{
+       set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+       irq_enable_hazard();
+}
+
+ /* For MIPS IRQs which shared by all cores */
+static struct irq_chip loongson_irq_chip = {
+       .name           = "Loongson",
+       .irq_ack        = mask_loongson_irq,
+       .irq_mask       = mask_loongson_irq,
+       .irq_mask_ack   = mask_loongson_irq,
+       .irq_unmask     = unmask_loongson_irq,
+       .irq_eoi        = unmask_loongson_irq,
+};
+
+void irq_router_init(void)
+{
+       int i;
+
+       /* route LPC int to cpu core0 int 0 */
+       LOONGSON_INT_ROUTER_LPC = LOONGSON_INT_CORE0_INT0;
+       /* route HT1 int0 ~ int7 to cpu core0 INT1*/
+       for (i = 0; i < 8; i++)
+               LOONGSON_INT_ROUTER_HT1(i) = LOONGSON_INT_CORE0_INT1;
+       /* enable HT1 interrupt */
+       LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
+       /* enable router interrupt intenset */
+       LOONGSON_INT_ROUTER_INTENSET =
+               LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
+}
+
+void __init mach_init_irq(void)
+{
+       clear_c0_status(ST0_IM | ST0_BEV);
+
+       irq_router_init();
+       mips_cpu_irq_init();
+       init_i8259_irqs();
+       irq_set_chip_and_handler(LOONGSON_UART_IRQ,
+                       &loongson_irq_chip, handle_level_irq);
+
+       /* setup HT1 irq */
+       setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
+
+       set_c0_status(STATUSF_IP2 | STATUSF_IP6);
+}