Merge tag 'iwlwifi-next-for-kalle-2014-12-30' of https://git.kernel.org/pub/scm/linux...

[cascardo/linux.git] / arch / powerpc / include / asm / kvm_book3s_64.h

diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h
index d645428..2d81e20 100644 (file)
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -37,7 +37,6 @@ static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
 
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 #define KVM_DEFAULT_HPT_ORDER  24      /* 16MB HPT by default */
-extern unsigned long kvm_rma_pages;
 #endif
 
 #define VRMA_VSID      0x1ffffffUL     /* 1TB VSID reserved for VRMA */
@@ -59,20 +58,29 @@ extern unsigned long kvm_rma_pages;
 /* These bits are reserved in the guest view of the HPTE */
 #define HPTE_GR_RESERVED       HPTE_GR_MODIFIED
 
-static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)
+static inline long try_lock_hpte(__be64 *hpte, unsigned long bits)
 {
        unsigned long tmp, old;
+       __be64 be_lockbit, be_bits;
+
+       /*
+        * We load/store in native endian, but the HTAB is in big endian. If
+        * we byte swap all data we apply on the PTE we're implicitly correct
+        * again.
+        */
+       be_lockbit = cpu_to_be64(HPTE_V_HVLOCK);
+       be_bits = cpu_to_be64(bits);
 
        asm volatile("  ldarx   %0,0,%2\n"
                     "  and.    %1,%0,%3\n"
                     "  bne     2f\n"
-                    "  ori     %0,%0,%4\n"
+                    "  or      %0,%0,%4\n"
                     "  stdcx.  %0,0,%2\n"
                     "  beq+    2f\n"
                     "  mr      %1,%3\n"
                     "2:        isync"
                     : "=&r" (tmp), "=&r" (old)
-                    : "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
+                    : "r" (hpte), "r" (be_bits), "r" (be_lockbit)
                     : "cc", "memory");
        return old == 0;
 }
@@ -110,16 +118,12 @@ static inline int __hpte_actual_psize(unsigned int lp, int psize)
 static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
                                             unsigned long pte_index)
 {
-       int b_psize, a_psize;
+       int b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K;
        unsigned int penc;
        unsigned long rb = 0, va_low, sllp;
        unsigned int lp = (r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
 
-       if (!(v & HPTE_V_LARGE)) {
-               /* both base and actual psize is 4k */
-               b_psize = MMU_PAGE_4K;
-               a_psize = MMU_PAGE_4K;
-       } else {
+       if (v & HPTE_V_LARGE) {
                for (b_psize = 0; b_psize < MMU_PAGE_COUNT; b_psize++) {
 
                        /* valid entries have a shift value */
@@ -142,6 +146,8 @@ static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
         */
        /* This covers 14..54 bits of va*/
        rb = (v & ~0x7fUL) << 16;               /* AVA field */
+
+       rb |= (v >> HPTE_V_SSIZE_SHIFT) << 8;   /*  B field */
        /*
         * AVA in v had cleared lower 23 bits. We need to derive
         * that from pteg index
@@ -172,10 +178,10 @@ static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
        {
                int aval_shift;
                /*
-                * remaining 7bits of AVA/LP fields
+                * remaining bits of AVA/LP fields
                 * Also contain the rr bits of LP
                 */
-               rb |= (va_low & 0x7f) << 16;
+               rb |= (va_low << mmu_psize_defs[b_psize].shift) & 0x7ff000;
                /*
                 * Now clear not needed LP bits based on actual psize
                 */