powerpc: tm: Rename transct_(*) to ck(\1)_state

[cascardo/linux.git] / arch / powerpc / kernel / tm.S

diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
index 298afcf..3a2d041 100644 (file)
--- a/arch/powerpc/kernel/tm.S
+++ b/arch/powerpc/kernel/tm.S
@@ -108,6 +108,7 @@ _GLOBAL(tm_reclaim)
        /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
 
        std     r3, STK_PARAM(R3)(r1)
+       std     r4, STK_PARAM(R4)(r1)
        SAVE_NVGPRS(r1)
 
        /* We need to setup MSR for VSX register save instructions. */
@@ -126,43 +127,6 @@ _GLOBAL(tm_reclaim)
        mtmsrd  r15
        std     r14, TM_FRAME_L0(r1)
 
-       /* Stash the stack pointer away for use after reclaim */
-       std     r1, PACAR1(r13)
-
-       /* ******************** FPR/VR/VSRs ************
-        * Before reclaiming, capture the current/transactional FPR/VR
-       * versions /if used/.
-        *
-        * (If VSX used, FP and VMX are implied.  Or, we don't need to look
-        * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
-        *
-        * We're passed the thread's MSR as parameter 2.
-        *
-        * We enabled VEC/FP/VSX in the msr above, so we can execute these
-        * instructions!
-        */
-       andis.          r0, r4, MSR_VEC@h
-       beq     dont_backup_vec
-
-       addi    r7, r3, THREAD_TRANSACT_VRSTATE
-       SAVE_32VRS(0, r6, r7)   /* r6 scratch, r7 transact vr state */
-       mfvscr  v0
-       li      r6, VRSTATE_VSCR
-       stvx    v0, r7, r6
-dont_backup_vec:
-       mfspr   r0, SPRN_VRSAVE
-       std     r0, THREAD_TRANSACT_VRSAVE(r3)
-
-       andi.   r0, r4, MSR_FP
-       beq     dont_backup_fp
-
-       addi    r7, r3, THREAD_TRANSACT_FPSTATE
-       SAVE_32FPRS_VSRS(0, R6, R7)     /* r6 scratch, r7 transact fp state */
-
-       mffs    fr0
-       stfd    fr0,FPSTATE_FPSCR(r7)
-
-dont_backup_fp:
        /* Do sanity check on MSR to make sure we are suspended */
        li      r7, (MSR_TS_S)@higher
        srdi    r6, r14, 32
@@ -170,6 +134,9 @@ dont_backup_fp:
 1:     tdeqi   r6, 0
        EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
 
+       /* Stash the stack pointer away for use after reclaim */
+       std     r1, PACAR1(r13)
+
        /* Clear MSR RI since we are about to change r1, EE is already off. */
        li      r4, 0
        mtmsrd  r4, 1
@@ -273,6 +240,43 @@ dont_backup_fp:
         * MSR.
         */
 
+
+       /* ******************** FPR/VR/VSRs ************
+        * After reclaiming, capture the checkpointed FPRs/VRs /if used/.
+        *
+        * (If VSX used, FP and VMX are implied.  Or, we don't need to look
+        * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
+        *
+        * We're passed the thread's MSR as the second parameter
+        *
+        * We enabled VEC/FP/VSX in the msr above, so we can execute these
+        * instructions!
+        */
+       ld      r4, STK_PARAM(R4)(r1)           /* Second parameter, MSR * */
+       mr      r3, r12
+       andis.          r0, r4, MSR_VEC@h
+       beq     dont_backup_vec
+
+       addi    r7, r3, THREAD_CKVRSTATE
+       SAVE_32VRS(0, r6, r7)   /* r6 scratch, r7 transact vr state */
+       mfvscr  v0
+       li      r6, VRSTATE_VSCR
+       stvx    v0, r7, r6
+dont_backup_vec:
+       mfspr   r0, SPRN_VRSAVE
+       std     r0, THREAD_CKVRSAVE(r3)
+
+       andi.   r0, r4, MSR_FP
+       beq     dont_backup_fp
+
+       addi    r7, r3, THREAD_CKFPSTATE
+       SAVE_32FPRS_VSRS(0, R6, R7)     /* r6 scratch, r7 transact fp state */
+
+       mffs    fr0
+       stfd    fr0,FPSTATE_FPSCR(r7)
+
+dont_backup_fp:
+
        /* TM regs, incl TEXASR -- these live in thread_struct.  Note they've
         * been updated by the treclaim, to explain to userland the failure
         * cause (aborted).
@@ -288,6 +292,7 @@ dont_backup_fp:
 
        /* Restore original MSR/IRQ state & clear TM mode */
        ld      r14, TM_FRAME_L0(r1)            /* Orig MSR */
+
        li      r15, 0
        rldimi  r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
        mtmsrd  r14
@@ -356,28 +361,29 @@ _GLOBAL(__tm_recheckpoint)
        mtmsr   r5
 
 #ifdef CONFIG_ALTIVEC
-       /* FP and VEC registers:  These are recheckpointed from thread.fpr[]
-        * and thread.vr[] respectively.  The thread.transact_fpr[] version
-        * is more modern, and will be loaded subsequently by any FPUnavailable
-        * trap.
+       /*
+        * FP and VEC registers: These are recheckpointed from
+        * thread.ckfp_state and thread.ckvr_state respectively. The
+        * thread.fp_state[] version holds the 'live' (transactional)
+        * and will be loaded subsequently by any FPUnavailable trap.
         */
        andis.  r0, r4, MSR_VEC@h
        beq     dont_restore_vec
 
-       addi    r8, r3, THREAD_VRSTATE
+       addi    r8, r3, THREAD_CKVRSTATE
        li      r5, VRSTATE_VSCR
        lvx     v0, r8, r5
        mtvscr  v0
        REST_32VRS(0, r5, r8)                   /* r5 scratch, r8 ptr */
 dont_restore_vec:
-       ld      r5, THREAD_VRSAVE(r3)
+       ld      r5, THREAD_CKVRSAVE(r3)
        mtspr   SPRN_VRSAVE, r5
 #endif
 
        andi.   r0, r4, MSR_FP
        beq     dont_restore_fp
 
-       addi    r8, r3, THREAD_FPSTATE
+       addi    r8, r3, THREAD_CKFPSTATE
        lfd     fr0, FPSTATE_FPSCR(r8)
        MTFSF_L(fr0)
        REST_32FPRS_VSRS(0, R4, R8)