powerpc/mm: Free up _PAGE_COHERENCE for numa fault use later

[cascardo/linux.git] / arch / powerpc / mm / hash_low_64.S

diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index d3cbda6..1136d26 100644 (file)
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -148,7 +148,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
        andc    r0,r30,r0               /* r0 = pte & ~r0 */
        rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-       ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
+       /*
+        * Always add "C" bit for perf. Memory coherence is always enabled
+        */
+       ori     r3,r3,HPTE_R_C | HPTE_R_M
 
        /* We eventually do the icache sync here (maybe inline that
         * code rather than call a C function...) 
@@ -457,7 +460,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
        andc    r0,r3,r0                /* r0 = pte & ~r0 */
        rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-       ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
+       /*
+        * Always add "C" bit for perf. Memory coherence is always enabled
+        */
+       ori     r3,r3,HPTE_R_C | HPTE_R_M
 
        /* We eventually do the icache sync here (maybe inline that
         * code rather than call a C function...)
@@ -795,7 +801,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
        andc    r0,r30,r0               /* r0 = pte & ~r0 */
        rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-       ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
+       /*
+        * Always add "C" bit for perf. Memory coherence is always enabled
+        */
+       ori     r3,r3,HPTE_R_C | HPTE_R_M
 
        /* We eventually do the icache sync here (maybe inline that
         * code rather than call a C function...)