Merge tag 'powerpc-4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...

[cascardo/linux.git] / arch / powerpc / mm / hash_utils_64.c

diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index ef3ae89..90480e2 100644 (file)
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -766,6 +766,29 @@ int remove_section_mapping(unsigned long start, unsigned long end)
 }
 #endif /* CONFIG_MEMORY_HOTPLUG */
 
+static void update_hid_for_hash(void)
+{
+       unsigned long hid0;
+       unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
+
+       asm volatile("ptesync": : :"memory");
+       /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
+       asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
+                    : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory");
+       asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
+       /*
+        * now switch the HID
+        */
+       hid0  = mfspr(SPRN_HID0);
+       hid0 &= ~HID0_POWER9_RADIX;
+       mtspr(SPRN_HID0, hid0);
+       asm volatile("isync": : :"memory");
+
+       /* Wait for it to happen */
+       while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
+               cpu_relax();
+}
+
 static void __init hash_init_partition_table(phys_addr_t hash_table,
                                             unsigned long htab_size)
 {
@@ -792,6 +815,8 @@ static void __init hash_init_partition_table(phys_addr_t hash_table,
         */
        partition_tb->patb1 = 0;
        pr_info("Partition table %p\n", partition_tb);
+       if (cpu_has_feature(CPU_FTR_POWER9_DD1))
+               update_hid_for_hash();
        /*
         * update partition table control register,
         * 64 K size.
@@ -1515,6 +1540,29 @@ out_exit:
        local_irq_restore(flags);
 }
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+static inline void tm_flush_hash_page(int local)
+{
+       /*
+        * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
+        * page back to a block device w/PIO could pick up transactional data
+        * (bad!) so we force an abort here. Before the sync the page will be
+        * made read-only, which will flush_hash_page. BIG ISSUE here: if the
+        * kernel uses a page from userspace without unmapping it first, it may
+        * see the speculated version.
+        */
+       if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
+           MSR_TM_ACTIVE(current->thread.regs->msr)) {
+               tm_enable();
+               tm_abort(TM_CAUSE_TLBI);
+       }
+}
+#else
+static inline void tm_flush_hash_page(int local)
+{
+}
+#endif
+
 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
  *          do not forget to update the assembly call site !
  */
@@ -1541,21 +1589,7 @@ void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
                                             ssize, local);
        } pte_iterate_hashed_end();
 
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-       /* Transactions are not aborted by tlbiel, only tlbie.
-        * Without, syncing a page back to a block device w/ PIO could pick up
-        * transactional data (bad!) so we force an abort here.  Before the
-        * sync the page will be made read-only, which will flush_hash_page.
-        * BIG ISSUE here: if the kernel uses a page from userspace without
-        * unmapping it first, it may see the speculated version.
-        */
-       if (local && cpu_has_feature(CPU_FTR_TM) &&
-           current->thread.regs &&
-           MSR_TM_ACTIVE(current->thread.regs->msr)) {
-               tm_enable();
-               tm_abort(TM_CAUSE_TLBI);
-       }
-#endif
+       tm_flush_hash_page(local);
 }
 
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
@@ -1612,22 +1646,7 @@ void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
                                             MMU_PAGE_16M, ssize, local);
        }
 tm_abort:
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-       /* Transactions are not aborted by tlbiel, only tlbie.
-        * Without, syncing a page back to a block device w/ PIO could pick up
-        * transactional data (bad!) so we force an abort here.  Before the
-        * sync the page will be made read-only, which will flush_hash_page.
-        * BIG ISSUE here: if the kernel uses a page from userspace without
-        * unmapping it first, it may see the speculated version.
-        */
-       if (local && cpu_has_feature(CPU_FTR_TM) &&
-           current->thread.regs &&
-           MSR_TM_ACTIVE(current->thread.regs->msr)) {
-               tm_enable();
-               tm_abort(TM_CAUSE_TLBI);
-       }
-#endif
-       return;
+       tm_flush_hash_page(local);
 }
 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */