Merge branch 'sfi' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux into...

[cascardo/linux.git] / arch / x86 / include / uapi / asm / msr-index.h

diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 4f6dae6..d11e1c5 100644 (file)
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -152,6 +152,45 @@
 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
 
+/* Hardware P state interface */
+#define MSR_PPERF                      0x0000064e
+#define MSR_PERF_LIMIT_REASONS         0x0000064f
+#define MSR_PM_ENABLE                  0x00000770
+#define MSR_HWP_CAPABILITIES           0x00000771
+#define MSR_HWP_REQUEST_PKG            0x00000772
+#define MSR_HWP_INTERRUPT              0x00000773
+#define MSR_HWP_REQUEST                0x00000774
+#define MSR_HWP_STATUS                 0x00000777
+
+/* CPUID.6.EAX */
+#define HWP_BASE_BIT                   (1<<7)
+#define HWP_NOTIFICATIONS_BIT          (1<<8)
+#define HWP_ACTIVITY_WINDOW_BIT                (1<<9)
+#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
+#define HWP_PACKAGE_LEVEL_REQUEST_BIT  (1<<11)
+
+/* IA32_HWP_CAPABILITIES */
+#define HWP_HIGHEST_PERF(x)            (x & 0xff)
+#define HWP_GUARANTEED_PERF(x)         ((x & (0xff << 8)) >>8)
+#define HWP_MOSTEFFICIENT_PERF(x)      ((x & (0xff << 16)) >>16)
+#define HWP_LOWEST_PERF(x)             ((x & (0xff << 24)) >>24)
+
+/* IA32_HWP_REQUEST */
+#define HWP_MIN_PERF(x)                (x & 0xff)
+#define HWP_MAX_PERF(x)                ((x & 0xff) << 8)
+#define HWP_DESIRED_PERF(x)            ((x & 0xff) << 16)
+#define HWP_ENERGY_PERF_PREFERENCE(x)  ((x & 0xff) << 24)
+#define HWP_ACTIVITY_WINDOW(x)         ((x & 0xff3) << 32)
+#define HWP_PACKAGE_CONTROL(x)         ((x & 0x1) << 42)
+
+/* IA32_HWP_STATUS */
+#define HWP_GUARANTEED_CHANGE(x)       (x & 0x1)
+#define HWP_EXCURSION_TO_MINIMUM(x)    (x & 0x4)
+
+/* IA32_HWP_INTERRUPT */
+#define HWP_CHANGE_TO_GUARANTEED_INT(x)        (x & 0x1)
+#define HWP_EXCURSION_TO_MINIMUM_INT(x)        (x & 0x2)
+
 #define MSR_AMD64_MC0_MASK             0xc0010044
 
 #define MSR_IA32_MCx_CTL(x)            (MSR_IA32_MC0_CTL + 4*(x))
@@ -206,6 +245,7 @@
 #define MSR_AMD64_IBSOP_REG_MASK       ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
 #define MSR_AMD64_IBSCTL               0xc001103a
 #define MSR_AMD64_IBSBRTARGET          0xc001103b
+#define MSR_AMD64_IBSOPDATA4           0xc001103d
 #define MSR_AMD64_IBS_REG_COUNT_MAX    8 /* includes MSR_AMD64_IBSBRTARGET */
 
 /* Fam 16h MSRs */
@@ -346,6 +386,8 @@
 
 #define MSR_IA32_TEMPERATURE_TARGET    0x000001a2
 
+#define MSR_MISC_PWR_MGMT              0x000001aa
+
 #define MSR_IA32_ENERGY_PERF_BIAS      0x000001b0
 #define ENERGY_PERF_BIAS_PERFORMANCE   0
 #define ENERGY_PERF_BIAS_NORMAL                6