Merge tag 'iwlwifi-next-for-kalle-2014-12-30' of https://git.kernel.org/pub/scm/linux...

[cascardo/linux.git] / drivers / clocksource / exynos_mct.c

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index ab51bf2..9403061 100644 (file)
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -94,7 +94,7 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
        u32 mask;
        u32 i;
 
-       __raw_writel(value, reg_base + offset);
+       writel_relaxed(value, reg_base + offset);
 
        if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
                stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
@@ -144,8 +144,8 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
 
        /* Wait maximum 1 ms until written values are applied */
        for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
-               if (__raw_readl(reg_base + stat_addr) & mask) {
-                       __raw_writel(mask, reg_base + stat_addr);
+               if (readl_relaxed(reg_base + stat_addr) & mask) {
+                       writel_relaxed(mask, reg_base + stat_addr);
                        return;
                }
 
@@ -157,28 +157,51 @@ static void exynos4_mct_frc_start(void)
 {
        u32 reg;
 
-       reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+       reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
        reg |= MCT_G_TCON_START;
        exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 }
 
-static cycle_t notrace _exynos4_frc_read(void)
+/**
+ * exynos4_read_count_64 - Read all 64-bits of the global counter
+ *
+ * This will read all 64-bits of the global counter taking care to make sure
+ * that the upper and lower half match.  Note that reading the MCT can be quite
+ * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
+ * only) version when possible.
+ *
+ * Returns the number of cycles in the global counter.
+ */
+static u64 exynos4_read_count_64(void)
 {
        unsigned int lo, hi;
-       u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
+       u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
 
        do {
                hi = hi2;
-               lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
-               hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
+               lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
+               hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
        } while (hi != hi2);
 
        return ((cycle_t)hi << 32) | lo;
 }
 
+/**
+ * exynos4_read_count_32 - Read the lower 32-bits of the global counter
+ *
+ * This will read just the lower 32-bits of the global counter.  This is marked
+ * as notrace so it can be used by the scheduler clock.
+ *
+ * Returns the number of cycles in the global counter (lower 32 bits).
+ */
+static u32 notrace exynos4_read_count_32(void)
+{
+       return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
+}
+
 static cycle_t exynos4_frc_read(struct clocksource *cs)
 {
-       return _exynos4_frc_read();
+       return exynos4_read_count_32();
 }
 
 static void exynos4_frc_resume(struct clocksource *cs)
@@ -190,21 +213,23 @@ struct clocksource mct_frc = {
        .name           = "mct-frc",
        .rating         = 400,
        .read           = exynos4_frc_read,
-       .mask           = CLOCKSOURCE_MASK(64),
+       .mask           = CLOCKSOURCE_MASK(32),
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
        .resume         = exynos4_frc_resume,
 };
 
 static u64 notrace exynos4_read_sched_clock(void)
 {
-       return _exynos4_frc_read();
+       return exynos4_read_count_32();
 }
 
 static struct delay_timer exynos4_delay_timer;
 
 static cycles_t exynos4_read_current_timer(void)
 {
-       return _exynos4_frc_read();
+       BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32),
+                        "cycles_t needs to move to 32-bit for ARM64 usage");
+       return exynos4_read_count_32();
 }
 
 static void __init exynos4_clocksource_init(void)
@@ -218,14 +243,14 @@ static void __init exynos4_clocksource_init(void)
        if (clocksource_register_hz(&mct_frc, clk_rate))
                panic("%s: can't register clocksource\n", mct_frc.name);
 
-       sched_clock_register(exynos4_read_sched_clock, 64, clk_rate);
+       sched_clock_register(exynos4_read_sched_clock, 32, clk_rate);
 }
 
 static void exynos4_mct_comp0_stop(void)
 {
        unsigned int tcon;
 
-       tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+       tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
        tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
 
        exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
@@ -238,14 +263,14 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode,
        unsigned int tcon;
        cycle_t comp_cycle;
 
-       tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+       tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
 
        if (mode == CLOCK_EVT_MODE_PERIODIC) {
                tcon |= MCT_G_TCON_COMP0_AUTO_INC;
                exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
        }
 
-       comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
+       comp_cycle = exynos4_read_count_64() + cycles;
        exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
        exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
 
@@ -327,7 +352,7 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
        unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
        unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
 
-       tmp = __raw_readl(reg_base + offset);
+       tmp = readl_relaxed(reg_base + offset);
        if (tmp & mask) {
                tmp &= ~mask;
                exynos4_mct_write(tmp, offset);
@@ -349,7 +374,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
        /* enable MCT tick interrupt */
        exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
 
-       tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
+       tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
        tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
               MCT_L_TCON_INTERVAL_MODE;
        exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
@@ -401,7 +426,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
                exynos4_mct_tick_stop(mevt);
 
        /* Clear the MCT tick interrupt */
-       if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+       if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
                exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
                return 1;
        } else {