Merge tag 'drm-intel-next-2015-02-14' of git://anongit.freedesktop.org/drm-intel...

[cascardo/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e758c05..d17e76d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2319,6 +2319,14 @@ static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
        cmd = MI_FLUSH_DW;
        if (INTEL_INFO(ring->dev)->gen >= 8)
                cmd += 1;
+
+       /* We always require a command barrier so that subsequent
+        * commands, such as breadcrumb interrupts, are strictly ordered
+        * wrt the contents of the write cache being flushed to memory
+        * (and thus being coherent from the CPU).
+        */
+       cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
+
        /*
         * Bspec vol 1c.5 - video engine command streamer:
         * "If ENABLED, all TLBs will be invalidated once the flush
@@ -2326,8 +2334,8 @@ static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
         * Post-Sync Operation field is a value of 1h or 3h."
         */
        if (invalidate & I915_GEM_GPU_DOMAINS)
-               cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
-                       MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
+               cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
+
        intel_ring_emit(ring, cmd);
        intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
        if (INTEL_INFO(ring->dev)->gen >= 8) {
@@ -2423,6 +2431,14 @@ static int gen6_ring_flush(struct intel_engine_cs *ring,
        cmd = MI_FLUSH_DW;
        if (INTEL_INFO(ring->dev)->gen >= 8)
                cmd += 1;
+
+       /* We always require a command barrier so that subsequent
+        * commands, such as breadcrumb interrupts, are strictly ordered
+        * wrt the contents of the write cache being flushed to memory
+        * (and thus being coherent from the CPU).
+        */
+       cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
+
        /*
         * Bspec vol 1c.3 - blitter engine command streamer:
         * "If ENABLED, all TLBs will be invalidated once the flush
@@ -2430,8 +2446,7 @@ static int gen6_ring_flush(struct intel_engine_cs *ring,
         * Post-Sync Operation field is a value of 1h or 3h."
         */
        if (invalidate & I915_GEM_DOMAIN_RENDER)
-               cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
-                       MI_FLUSH_DW_OP_STOREDW;
+               cmd |= MI_INVALIDATE_TLB;
        intel_ring_emit(ring, cmd);
        intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
        if (INTEL_INFO(ring->dev)->gen >= 8) {