Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

[cascardo/linux.git] / drivers / net / ethernet / cavium / thunder / nic.h

diff --git a/drivers/net/ethernet/cavium/thunder/nic.h b/drivers/net/ethernet/cavium/thunder/nic.h
index e29815d..18d12d3 100644 (file)
--- a/drivers/net/ethernet/cavium/thunder/nic.h
+++ b/drivers/net/ethernet/cavium/thunder/nic.h
@@ -20,6 +20,17 @@
 #define        PCI_DEVICE_ID_THUNDER_NIC_VF            0xA034
 #define        PCI_DEVICE_ID_THUNDER_BGX               0xA026
 
+/* Subsystem device IDs */
+#define PCI_SUBSYS_DEVID_88XX_NIC_PF           0xA11E
+#define PCI_SUBSYS_DEVID_81XX_NIC_PF           0xA21E
+#define PCI_SUBSYS_DEVID_83XX_NIC_PF           0xA31E
+
+#define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF     0xA11E
+#define PCI_SUBSYS_DEVID_88XX_NIC_VF           0xA134
+#define PCI_SUBSYS_DEVID_81XX_NIC_VF           0xA234
+#define PCI_SUBSYS_DEVID_83XX_NIC_VF           0xA334
+
+
 /* PCI BAR nos */
 #define        PCI_CFG_REG_BAR_NUM             0
 #define        PCI_MSIX_REG_BAR_NUM            4
@@ -41,40 +52,8 @@
 /* Max pkinds */
 #define        NIC_MAX_PKIND                   16
 
-/* Rx Channels */
-/* Receive channel configuration in TNS bypass mode
- * Below is configuration in TNS bypass mode
- * BGX0-LMAC0-CHAN0 - VNIC CHAN0
- * BGX0-LMAC1-CHAN0 - VNIC CHAN16
- * ...
- * BGX1-LMAC0-CHAN0 - VNIC CHAN128
- * ...
- * BGX1-LMAC3-CHAN0 - VNIC CHAN174
- */
-#define        NIC_INTF_COUNT                  2  /* Interfaces btw VNIC and TNS/BGX */
-#define        NIC_CHANS_PER_INF               128
-#define        NIC_MAX_CHANS                   (NIC_INTF_COUNT * NIC_CHANS_PER_INF)
-#define        NIC_CPI_COUNT                   2048 /* No of channel parse indices */
-
-/* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */
-#define NIC_MAX_BGX                    MAX_BGX_PER_CN88XX
-#define        NIC_CPI_PER_BGX                 (NIC_CPI_COUNT / NIC_MAX_BGX)
-#define        NIC_MAX_CPI_PER_LMAC            64 /* Max when CPI_ALG is IP diffserv */
-#define        NIC_RSSI_PER_BGX                (NIC_RSSI_COUNT / NIC_MAX_BGX)
-
-/* Tx scheduling */
-#define        NIC_MAX_TL4                     1024
-#define        NIC_MAX_TL4_SHAPERS             256 /* 1 shaper for 4 TL4s */
-#define        NIC_MAX_TL3                     256
-#define        NIC_MAX_TL3_SHAPERS             64  /* 1 shaper for 4 TL3s */
-#define        NIC_MAX_TL2                     64
-#define        NIC_MAX_TL2_SHAPERS             2  /* 1 shaper for 32 TL2s */
-#define        NIC_MAX_TL1                     2
-
-/* TNS bypass mode */
-#define        NIC_TL2_PER_BGX                 32
-#define        NIC_TL4_PER_BGX                 (NIC_MAX_TL4 / NIC_MAX_BGX)
-#define        NIC_TL4_PER_LMAC                (NIC_MAX_TL4 / NIC_CHANS_PER_INF)
+/* Max when CPI_ALG is IP diffserv */
+#define        NIC_MAX_CPI_PER_LMAC            64
 
 /* NIC VF Interrupts */
 #define        NICVF_INTR_CQ                   0
@@ -148,7 +127,6 @@ struct nicvf_cq_poll {
        struct  napi_struct napi;
 };
 
-#define        NIC_RSSI_COUNT                  4096 /* Total no of RSS indices */
 #define NIC_MAX_RSS_HASH_BITS          8
 #define NIC_MAX_RSS_IDR_TBL_SIZE       (1 << NIC_MAX_RSS_HASH_BITS)
 #define RSS_HASH_KEY_SIZE              5 /* 320 bit key */
@@ -273,6 +251,7 @@ struct nicvf {
        struct net_device       *netdev;
        struct pci_dev          *pdev;
        void __iomem            *reg_base;
+#define        MAX_QUEUES_PER_QSET                     8
        struct queue_set        *qs;
        struct nicvf_cq_poll    *napi[8];
        u8                      vf_id;
@@ -369,6 +348,7 @@ struct nicvf {
 #define        NIC_MBOX_MSG_PNICVF_PTR         0x14    /* Get primary qset nicvf ptr */
 #define        NIC_MBOX_MSG_SNICVF_PTR         0x15    /* Send sqet nicvf ptr to PVF */
 #define        NIC_MBOX_MSG_LOOPBACK           0x16    /* Set interface in loopback */
+#define        NIC_MBOX_MSG_RESET_STAT_COUNTER 0x17    /* Reset statistics counters */
 #define        NIC_MBOX_MSG_CFG_DONE           0xF0    /* VF configuration done */
 #define        NIC_MBOX_MSG_SHUTDOWN           0xF1    /* VF is being shutdown */
 
@@ -485,6 +465,31 @@ struct set_loopback {
        bool  enable;
 };
 
+/* Reset statistics counters */
+struct reset_stat_cfg {
+       u8    msg;
+       /* Bitmap to select NIC_PF_VNIC(vf_id)_RX_STAT(0..13) */
+       u16   rx_stat_mask;
+       /* Bitmap to select NIC_PF_VNIC(vf_id)_TX_STAT(0..4) */
+       u8    tx_stat_mask;
+       /* Bitmap to select NIC_PF_QS(0..127)_RQ(0..7)_STAT(0..1)
+        * bit14, bit15 NIC_PF_QS(vf_id)_RQ7_STAT(0..1)
+        * bit12, bit13 NIC_PF_QS(vf_id)_RQ6_STAT(0..1)
+        * ..
+        * bit2, bit3 NIC_PF_QS(vf_id)_RQ1_STAT(0..1)
+        * bit0, bit1 NIC_PF_QS(vf_id)_RQ0_STAT(0..1)
+        */
+       u16   rq_stat_mask;
+       /* Bitmap to select NIC_PF_QS(0..127)_SQ(0..7)_STAT(0..1)
+        * bit14, bit15 NIC_PF_QS(vf_id)_SQ7_STAT(0..1)
+        * bit12, bit13 NIC_PF_QS(vf_id)_SQ6_STAT(0..1)
+        * ..
+        * bit2, bit3 NIC_PF_QS(vf_id)_SQ1_STAT(0..1)
+        * bit0, bit1 NIC_PF_QS(vf_id)_SQ0_STAT(0..1)
+        */
+       u16   sq_stat_mask;
+};
+
 /* 128 bit shared memory between PF and each VF */
 union nic_mbx {
        struct { u8 msg; }      msg;
@@ -502,6 +507,7 @@ union nic_mbx {
        struct sqs_alloc        sqs_alloc;
        struct nicvf_ptr        nicvf;
        struct set_loopback     lbk;
+       struct reset_stat_cfg   reset_stat;
 };
 
 #define NIC_NODE_ID_MASK       0x03
@@ -515,7 +521,14 @@ static inline int nic_get_node_id(struct pci_dev *pdev)
 
 static inline bool pass1_silicon(struct pci_dev *pdev)
 {
-       return pdev->revision < 8;
+       return (pdev->revision < 8) &&
+               (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF);
+}
+
+static inline bool pass2_silicon(struct pci_dev *pdev)
+{
+       return (pdev->revision >= 8) &&
+               (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF);
 }
 
 int nicvf_set_real_num_queues(struct net_device *netdev,