ath10k: add TARGET values for 10.x firmware

[cascardo/linux.git] / drivers / net / wireless / ath / ath10k / hw.h

diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h
index 5708888..2de13db 100644 (file)
--- a/drivers/net/wireless/ath/ath10k/hw.h
+++ b/drivers/net/wireless/ath/ath10k/hw.h
@@ -20,14 +20,12 @@
 
 #include "targaddrs.h"
 
-/* Supported FW version */
-#define SUPPORTED_FW_MAJOR     1
-#define SUPPORTED_FW_MINOR     0
-#define SUPPORTED_FW_RELEASE   0
-#define SUPPORTED_FW_BUILD     636
+/* QCA988X 1.0 definitions (unsupported) */
+#define QCA988X_HW_1_0_CHIP_ID_REV     0x0
 
 /* QCA988X 2.0 definitions */
 #define QCA988X_HW_2_0_VERSION         0x4100016c
+#define QCA988X_HW_2_0_CHIP_ID_REV     0x2
 #define QCA988X_HW_2_0_FW_DIR          "ath10k/QCA988X/hw2.0"
 #define QCA988X_HW_2_0_FW_FILE         "firmware.bin"
 #define QCA988X_HW_2_0_OTP_FILE                "otp.bin"
@@ -55,6 +53,7 @@ enum ath10k_mcast2ucast_mode {
        ATH10K_MCAST2UCAST_ENABLED = 1,
 };
 
+/* Target specific defines for MAIN firmware */
 #define TARGET_NUM_VDEVS                       8
 #define TARGET_NUM_PEER_AST                    2
 #define TARGET_NUM_WDS_ENTRIES                 32
@@ -70,7 +69,11 @@ enum ath10k_mcast2ucast_mode {
 #define TARGET_RX_CHAIN_MASK                   (BIT(0) | BIT(1) | BIT(2))
 #define TARGET_RX_TIMEOUT_LO_PRI               100
 #define TARGET_RX_TIMEOUT_HI_PRI               40
-#define TARGET_RX_DECAP_MODE                   ATH10K_HW_TXRX_ETHERNET
+
+/* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and
+ * avoid a very expensive re-alignment in mac80211. */
+#define TARGET_RX_DECAP_MODE                   ATH10K_HW_TXRX_NATIVE_WIFI
+
 #define TARGET_SCAN_MAX_PENDING_REQS           4
 #define TARGET_BMISS_OFFLOAD_MAX_VDEV          3
 #define TARGET_ROAM_OFFLOAD_MAX_VDEV           3
@@ -85,6 +88,36 @@ enum ath10k_mcast2ucast_mode {
 #define TARGET_NUM_MSDU_DESC                   (1024 + 400)
 #define TARGET_MAX_FRAG_ENTRIES                        0
 
+/* Target specific defines for 10.X firmware */
+#define TARGET_10X_NUM_VDEVS                   16
+#define TARGET_10X_NUM_PEER_AST                        2
+#define TARGET_10X_NUM_WDS_ENTRIES             32
+#define TARGET_10X_DMA_BURST_SIZE              0
+#define TARGET_10X_MAC_AGGR_DELIM              0
+#define TARGET_10X_AST_SKID_LIMIT              16
+#define TARGET_10X_NUM_PEERS                   (128 + (TARGET_10X_NUM_VDEVS))
+#define TARGET_10X_NUM_OFFLOAD_PEERS           0
+#define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS    0
+#define TARGET_10X_NUM_PEER_KEYS               2
+#define TARGET_10X_NUM_TIDS                    256
+#define TARGET_10X_TX_CHAIN_MASK               (BIT(0) | BIT(1) | BIT(2))
+#define TARGET_10X_RX_CHAIN_MASK               (BIT(0) | BIT(1) | BIT(2))
+#define TARGET_10X_RX_TIMEOUT_LO_PRI           100
+#define TARGET_10X_RX_TIMEOUT_HI_PRI           40
+#define TARGET_10X_RX_DECAP_MODE               ATH10K_HW_TXRX_ETHERNET
+#define TARGET_10X_SCAN_MAX_PENDING_REQS       4
+#define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV      2
+#define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV       2
+#define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES        8
+#define TARGET_10X_GTK_OFFLOAD_MAX_VDEV                3
+#define TARGET_10X_NUM_MCAST_GROUPS            0
+#define TARGET_10X_NUM_MCAST_TABLE_ELEMS       0
+#define TARGET_10X_MCAST2UCAST_MODE            ATH10K_MCAST2UCAST_DISABLED
+#define TARGET_10X_TX_DBG_LOG_SIZE             1024
+#define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
+#define TARGET_10X_VOW_CONFIG                  0
+#define TARGET_10X_NUM_MSDU_DESC               (1024 + 400)
+#define TARGET_10X_MAX_FRAG_ENTRIES            0
 
 /* Number of Copy Engines supported */
 #define CE_COUNT 8
@@ -164,6 +197,10 @@ enum ath10k_mcast2ucast_mode {
 #define SOC_LPO_CAL_ENABLE_LSB                 20
 #define SOC_LPO_CAL_ENABLE_MASK                        0x00100000
 
+#define SOC_CHIP_ID_ADDRESS                    0x000000ec
+#define SOC_CHIP_ID_REV_LSB                    8
+#define SOC_CHIP_ID_REV_MASK                   0x00000f00
+
 #define WLAN_RESET_CONTROL_COLD_RST_MASK       0x00000008
 #define WLAN_RESET_CONTROL_WARM_RST_MASK       0x00000004
 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB          0