ath10k: convert ath10k_pci_wake() to return

[cascardo/linux.git] / drivers / net / wireless / ath / ath10k / pci.h

diff --git a/drivers/net/wireless/ath/ath10k/pci.h b/drivers/net/wireless/ath/ath10k/pci.h
index 021172c..7c49f6f 100644 (file)
--- a/drivers/net/wireless/ath/ath10k/pci.h
+++ b/drivers/net/wireless/ath/ath10k/pci.h
@@ -52,9 +52,9 @@ enum ath10k_pci_compl_state {
 struct ath10k_pci_compl {
        struct list_head list;
        enum ath10k_pci_compl_state state;
-       struct ce_state *ce_state;
+       struct ath10k_ce_pipe *ce_state;
        struct ath10k_pci_pipe *pipe_info;
-       void *transfer_context;
+       struct sk_buff *skb;
        unsigned int nbytes;
        unsigned int transfer_id;
        unsigned int flags;
@@ -162,7 +162,7 @@ enum ath10k_pci_features {
 /* Per-pipe state. */
 struct ath10k_pci_pipe {
        /* Handle of underlying Copy Engine */
-       struct ce_state *ce_hdl;
+       struct ath10k_ce_pipe *ce_hdl;
 
        /* Our pipe number; facilitiates use of pipe_info ptrs. */
        u8 pipe_num;
@@ -190,7 +190,6 @@ struct ath10k_pci {
        struct device *dev;
        struct ath10k *ar;
        void __iomem *mem;
-       int cacheline_sz;
 
        DECLARE_BITMAP(features, ATH10K_PCI_FEATURE_COUNT);
 
@@ -227,13 +226,13 @@ struct ath10k_pci {
        u32 fw_indicator_address;
 
        /* Copy Engine used for Diagnostic Accesses */
-       struct ce_state *ce_diag;
+       struct ath10k_ce_pipe *ce_diag;
 
        /* FIXME: document what this really protects */
        spinlock_t ce_lock;
 
        /* Map CE id to ce_state */
-       struct ce_state ce_states[CE_COUNT_MAX];
+       struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
 };
 
 static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
@@ -241,14 +240,18 @@ static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
        return ar->hif.priv;
 }
 
-static inline u32 ath10k_pci_reg_read32(void __iomem *mem, u32 addr)
+static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
 {
-       return ioread32(mem + PCIE_LOCAL_BASE_ADDRESS + addr);
+       struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
+
+       return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
 }
 
-static inline void ath10k_pci_reg_write32(void __iomem *mem, u32 addr, u32 val)
+static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
 {
-       iowrite32(val, mem + PCIE_LOCAL_BASE_ADDRESS + addr);
+       struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
+
+       iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
 }
 
 #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
@@ -318,15 +321,17 @@ static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
        return ioread32(ar_pci->mem + offset);
 }
 
-void ath10k_do_pci_wake(struct ath10k *ar);
+int ath10k_do_pci_wake(struct ath10k *ar);
 void ath10k_do_pci_sleep(struct ath10k *ar);
 
-static inline void ath10k_pci_wake(struct ath10k *ar)
+static inline int ath10k_pci_wake(struct ath10k *ar)
 {
        struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 
        if (test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
-               ath10k_do_pci_wake(ar);
+               return ath10k_do_pci_wake(ar);
+
+       return 0;
 }
 
 static inline void ath10k_pci_sleep(struct ath10k *ar)