Merge branches 'pci/host-aardvark', 'pci/host-altera', 'pci/host-artpec', 'pci/host...

[cascardo/linux.git] / drivers / pci / host / pcie-xilinx-nwl.c

diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index 0b597d9..67eae41 100644 (file)
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -15,7 +15,7 @@
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/init.h>
 #include <linux/msi.h>
 #include <linux/of_address.h>
 #include <linux/of_pci.h>
@@ -85,10 +85,15 @@
 #define MSGF_MISC_SR_MASTER_ERR                BIT(5)
 #define MSGF_MISC_SR_I_ADDR_ERR                BIT(6)
 #define MSGF_MISC_SR_E_ADDR_ERR                BIT(7)
-#define MSGF_MISC_SR_UR_DETECT          BIT(20)
-
-#define MSGF_MISC_SR_PCIE_CORE         GENMASK(18, 16)
-#define MSGF_MISC_SR_PCIE_CORE_ERR     GENMASK(31, 22)
+#define MSGF_MISC_SR_FATAL_AER         BIT(16)
+#define MSGF_MISC_SR_NON_FATAL_AER     BIT(17)
+#define MSGF_MISC_SR_CORR_AER          BIT(18)
+#define MSGF_MISC_SR_UR_DETECT         BIT(20)
+#define MSGF_MISC_SR_NON_FATAL_DEV     BIT(22)
+#define MSGF_MISC_SR_FATAL_DEV         BIT(23)
+#define MSGF_MISC_SR_LINK_DOWN         BIT(24)
+#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH  BIT(25)
+#define MSGF_MSIC_SR_LINK_BWIDTH       BIT(26)
 
 #define MSGF_MISC_SR_MASKALL           (MSGF_MISC_SR_RXMSG_AVAIL | \
                                        MSGF_MISC_SR_RXMSG_OVER | \
@@ -96,9 +101,15 @@
                                        MSGF_MISC_SR_MASTER_ERR | \
                                        MSGF_MISC_SR_I_ADDR_ERR | \
                                        MSGF_MISC_SR_E_ADDR_ERR | \
+                                       MSGF_MISC_SR_FATAL_AER | \
+                                       MSGF_MISC_SR_NON_FATAL_AER | \
+                                       MSGF_MISC_SR_CORR_AER | \
                                        MSGF_MISC_SR_UR_DETECT | \
-                                       MSGF_MISC_SR_PCIE_CORE | \
-                                       MSGF_MISC_SR_PCIE_CORE_ERR)
+                                       MSGF_MISC_SR_NON_FATAL_DEV | \
+                                       MSGF_MISC_SR_FATAL_DEV | \
+                                       MSGF_MISC_SR_LINK_DOWN | \
+                                       MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
+                                       MSGF_MSIC_SR_LINK_BWIDTH)
 
 /* Legacy interrupt status mask bits */
 #define MSGF_LEG_SR_INTA               BIT(0)
@@ -109,8 +120,8 @@
                                        MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
 
 /* MSI interrupt status mask bits */
-#define MSGF_MSI_SR_LO_MASK            BIT(0)
-#define MSGF_MSI_SR_HI_MASK            BIT(0)
+#define MSGF_MSI_SR_LO_MASK            GENMASK(31, 0)
+#define MSGF_MSI_SR_HI_MASK            GENMASK(31, 0)
 
 #define MSII_PRESENT                   BIT(0)
 #define MSII_ENABLE                    BIT(0)
@@ -291,8 +302,29 @@ static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
                dev_err(pcie->dev,
                        "In Misc Egress address translation error\n");
 
-       if (misc_stat & MSGF_MISC_SR_PCIE_CORE_ERR)
-               dev_err(pcie->dev, "PCIe Core error\n");
+       if (misc_stat & MSGF_MISC_SR_FATAL_AER)
+               dev_err(pcie->dev, "Fatal Error in AER Capability\n");
+
+       if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
+               dev_err(pcie->dev, "Non-Fatal Error in AER Capability\n");
+
+       if (misc_stat & MSGF_MISC_SR_CORR_AER)
+               dev_err(pcie->dev, "Correctable Error in AER Capability\n");
+
+       if (misc_stat & MSGF_MISC_SR_UR_DETECT)
+               dev_err(pcie->dev, "Unsupported request Detected\n");
+
+       if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
+               dev_err(pcie->dev, "Non-Fatal Error Detected\n");
+
+       if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
+               dev_err(pcie->dev, "Fatal Error Detected\n");
+
+       if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
+               dev_info(pcie->dev, "Link Autonomous Bandwidth Management Status bit set\n");
+
+       if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
+               dev_info(pcie->dev, "Link Bandwidth Management Status bit set\n");
 
        /* Clear misc interrupt status */
        nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
@@ -459,40 +491,6 @@ static const struct irq_domain_ops dev_msi_domain_ops = {
        .free   = nwl_irq_domain_free,
 };
 
-static void nwl_msi_free_irq_domain(struct nwl_pcie *pcie)
-{
-       struct nwl_msi *msi = &pcie->msi;
-
-       if (msi->irq_msi0)
-               irq_set_chained_handler_and_data(msi->irq_msi0, NULL, NULL);
-       if (msi->irq_msi1)
-               irq_set_chained_handler_and_data(msi->irq_msi1, NULL, NULL);
-
-       if (msi->msi_domain)
-               irq_domain_remove(msi->msi_domain);
-       if (msi->dev_domain)
-               irq_domain_remove(msi->dev_domain);
-
-       kfree(msi->bitmap);
-       msi->bitmap = NULL;
-}
-
-static void nwl_pcie_free_irq_domain(struct nwl_pcie *pcie)
-{
-       int i;
-       u32 irq;
-
-       for (i = 0; i < INTX_NUM; i++) {
-               irq = irq_find_mapping(pcie->legacy_irq_domain, i + 1);
-               if (irq > 0)
-                       irq_dispose_mapping(irq);
-       }
-       if (pcie->legacy_irq_domain)
-               irq_domain_remove(pcie->legacy_irq_domain);
-
-       nwl_msi_free_irq_domain(pcie);
-}
-
 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
 {
 #ifdef CONFIG_PCI_MSI
@@ -867,25 +865,12 @@ error:
        return err;
 }
 
-static int nwl_pcie_remove(struct platform_device *pdev)
-{
-       struct nwl_pcie *pcie = platform_get_drvdata(pdev);
-
-       nwl_pcie_free_irq_domain(pcie);
-       platform_set_drvdata(pdev, NULL);
-       return 0;
-}
-
 static struct platform_driver nwl_pcie_driver = {
        .driver = {
                .name = "nwl-pcie",
+               .suppress_bind_attrs = true,
                .of_match_table = nwl_pcie_of_match,
        },
        .probe = nwl_pcie_probe,
-       .remove = nwl_pcie_remove,
 };
-module_platform_driver(nwl_pcie_driver);
-
-MODULE_AUTHOR("Xilinx, Inc");
-MODULE_DESCRIPTION("NWL PCIe driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver(nwl_pcie_driver);