#include "spi-fsl-lib.h"
/* eSPI Controller registers */
-struct fsl_espi_reg {
- __be32 mode; /* 0x000 - eSPI mode register */
- __be32 event; /* 0x004 - eSPI event register */
- __be32 mask; /* 0x008 - eSPI mask register */
- __be32 command; /* 0x00c - eSPI command register */
- __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
- __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
- u8 res[8]; /* 0x018 - 0x01c reserved */
- __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
-};
+#define ESPI_SPMODE 0x00 /* eSPI mode register */
+#define ESPI_SPIE 0x04 /* eSPI event register */
+#define ESPI_SPIM 0x08 /* eSPI mask register */
+#define ESPI_SPCOM 0x0c /* eSPI command register */
+#define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
+#define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
+#define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
+
+#define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)
/* eSPI Controller mode register definitions */
-#define SPMODE_ENABLE (1 << 31)
-#define SPMODE_LOOP (1 << 30)
+#define SPMODE_ENABLE BIT(31)
+#define SPMODE_LOOP BIT(30)
#define SPMODE_TXTHR(x) ((x) << 8)
#define SPMODE_RXTHR(x) ((x) << 0)
/* eSPI Controller CS mode register definitions */
-#define CSMODE_CI_INACTIVEHIGH (1 << 31)
-#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
-#define CSMODE_REV (1 << 29)
-#define CSMODE_DIV16 (1 << 28)
+#define CSMODE_CI_INACTIVEHIGH BIT(31)
+#define CSMODE_CP_BEGIN_EDGECLK BIT(30)
+#define CSMODE_REV BIT(29)
+#define CSMODE_DIV16 BIT(28)
#define CSMODE_PM(x) ((x) << 24)
-#define CSMODE_POL_1 (1 << 20)
+#define CSMODE_POL_1 BIT(20)
#define CSMODE_LEN(x) ((x) << 16)
#define CSMODE_BEF(x) ((x) << 12)
#define CSMODE_AFT(x) ((x) << 8)
| CSMODE_AFT(0) | CSMODE_CG(1))
/* SPIE register values */
-#define SPIE_NE 0x00000200 /* Not empty */
-#define SPIE_NF 0x00000100 /* Not full */
-
-/* SPIM register values */
-#define SPIM_NE 0x00000200 /* Not empty */
-#define SPIM_NF 0x00000100 /* Not full */
#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
+#define SPIE_TXE BIT(15) /* TX FIFO empty */
+#define SPIE_DON BIT(14) /* TX done */
+#define SPIE_RXT BIT(13) /* RX FIFO threshold */
+#define SPIE_RXF BIT(12) /* RX FIFO full */
+#define SPIE_TXT BIT(11) /* TX FIFO threshold*/
+#define SPIE_RNE BIT(9) /* RX FIFO not empty */
+#define SPIE_TNF BIT(8) /* TX FIFO not full */
+
+/* SPIM register values */
+#define SPIM_TXE BIT(15) /* TX FIFO empty */
+#define SPIM_DON BIT(14) /* TX done */
+#define SPIM_RXT BIT(13) /* RX FIFO threshold */
+#define SPIM_RXF BIT(12) /* RX FIFO full */
+#define SPIM_TXT BIT(11) /* TX FIFO threshold*/
+#define SPIM_RNE BIT(9) /* RX FIFO not empty */
+#define SPIM_TNF BIT(8) /* TX FIFO not full */
/* SPCOM register values */
#define SPCOM_CS(x) ((x) << 30)
+#define SPCOM_DO BIT(28) /* Dual output */
+#define SPCOM_TO BIT(27) /* TX only */
+#define SPCOM_RXSKIP(x) ((x) << 16)
#define SPCOM_TRANLEN(x) ((x) << 0)
+
#define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
#define AUTOSUSPEND_TIMEOUT 2000
+static inline u32 fsl_espi_read_reg(struct mpc8xxx_spi *mspi, int offset)
+{
+ return ioread32be(mspi->reg_base + offset);
+}
+
+static inline u8 fsl_espi_read_reg8(struct mpc8xxx_spi *mspi, int offset)
+{
+ return ioread8(mspi->reg_base + offset);
+}
+
+static inline void fsl_espi_write_reg(struct mpc8xxx_spi *mspi, int offset,
+ u32 val)
+{
+ iowrite32be(val, mspi->reg_base + offset);
+}
+
+static inline void fsl_espi_write_reg8(struct mpc8xxx_spi *mspi, int offset,
+ u8 val)
+{
+ iowrite8(val, mspi->reg_base + offset);
+}
+
static void fsl_espi_copy_to_buf(struct spi_message *m,
struct mpc8xxx_spi *mspi)
{
{
struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
struct spi_mpc8xxx_cs *cs = spi->controller_state;
- struct fsl_espi_reg *reg_base = mspi->reg_base;
- __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
- __be32 __iomem *espi_mode = ®_base->mode;
u32 tmp;
unsigned long flags;
local_irq_save(flags);
/* Turn off SPI unit prior changing mode */
- tmp = mpc8xxx_spi_read_reg(espi_mode);
- mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
- mpc8xxx_spi_write_reg(mode, cs->hw_mode);
- mpc8xxx_spi_write_reg(espi_mode, tmp);
+ tmp = fsl_espi_read_reg(mspi, ESPI_SPMODE);
+ fsl_espi_write_reg(mspi, ESPI_SPMODE, tmp & ~SPMODE_ENABLE);
+ fsl_espi_write_reg(mspi, ESPI_SPMODEx(spi->chip_select),
+ cs->hw_mode);
+ fsl_espi_write_reg(mspi, ESPI_SPMODE, tmp);
local_irq_restore(flags);
}
struct spi_transfer *t)
{
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
- int bits_per_word = 0;
+ int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
+ u32 hz = t ? t->speed_hz : spi->max_speed_hz;
u8 pm;
- u32 hz = 0;
struct spi_mpc8xxx_cs *cs = spi->controller_state;
- if (t) {
- bits_per_word = t->bits_per_word;
- hz = t->speed_hz;
- }
-
- /* spi_transfer level calls that work per-word */
- if (!bits_per_word)
- bits_per_word = spi->bits_per_word;
-
- if (!hz)
- hz = spi->max_speed_hz;
-
cs->rx_shift = 0;
cs->tx_shift = 0;
cs->get_rx = mpc8xxx_spi_rx_buf_u32;
static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
{
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
- struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
u32 word;
int ret;
reinit_completion(&mpc8xxx_spi->done);
/* Set SPCOM[CS] and SPCOM[TRANLEN] field */
- mpc8xxx_spi_write_reg(®_base->command,
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM,
(SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
/* enable rx ints */
- mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, SPIM_RNE);
/* transmit word */
word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
- mpc8xxx_spi_write_reg(®_base->transmit, word);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPITF, word);
/* Won't hang up forever, SPI bus sometimes got lost interrupts... */
ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ);
mpc8xxx_spi->count);
/* disable rx ints */
- mpc8xxx_spi_write_reg(®_base->mask, 0);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0);
return mpc8xxx_spi->count > 0 ? -EMSGSIZE : 0;
}
static int fsl_espi_setup(struct spi_device *spi)
{
struct mpc8xxx_spi *mpc8xxx_spi;
- struct fsl_espi_reg *reg_base;
- u32 hw_mode;
u32 loop_mode;
struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
}
mpc8xxx_spi = spi_master_get_devdata(spi->master);
- reg_base = mpc8xxx_spi->reg_base;
pm_runtime_get_sync(mpc8xxx_spi->dev);
- hw_mode = cs->hw_mode; /* Save original settings */
- cs->hw_mode = mpc8xxx_spi_read_reg(
- ®_base->csmode[spi->chip_select]);
+ cs->hw_mode = fsl_espi_read_reg(mpc8xxx_spi,
+ ESPI_SPMODEx(spi->chip_select));
/* mask out bits we are going to set */
cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
| CSMODE_REV);
cs->hw_mode |= CSMODE_REV;
/* Handle the loop mode */
- loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
+ loop_mode = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE);
loop_mode &= ~SPMODE_LOOP;
if (spi->mode & SPI_LOOP)
loop_mode |= SPMODE_LOOP;
- mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, loop_mode);
fsl_espi_setup_transfer(spi, NULL);
static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
{
- struct fsl_espi_reg *reg_base = mspi->reg_base;
-
/* We need handle RX first */
- if (events & SPIE_NE) {
+ if (events & SPIE_RNE) {
u32 rx_data, tmp;
u8 rx_data_8;
int rx_nr_bytes = 4;
if (SPIE_RXCNT(events) < min(4, mspi->len)) {
ret = spin_event_timeout(
!(SPIE_RXCNT(events =
- mpc8xxx_spi_read_reg(®_base->event)) <
+ fsl_espi_read_reg(mspi, ESPI_SPIE)) <
min(4, mspi->len)),
10000, 0); /* 10 msec */
if (!ret)
}
if (mspi->len >= 4) {
- rx_data = mpc8xxx_spi_read_reg(®_base->receive);
+ rx_data = fsl_espi_read_reg(mspi, ESPI_SPIRF);
} else if (mspi->len <= 0) {
dev_err(mspi->dev,
- "unexpected RX(SPIE_NE) interrupt occurred,\n"
+ "unexpected RX(SPIE_RNE) interrupt occurred,\n"
"(local rxlen %d bytes, reg rxlen %d bytes)\n",
min(4, mspi->len), SPIE_RXCNT(events));
rx_nr_bytes = 0;
tmp = mspi->len;
rx_data = 0;
while (tmp--) {
- rx_data_8 = in_8((u8 *)®_base->receive);
+ rx_data_8 = fsl_espi_read_reg8(mspi,
+ ESPI_SPIRF);
rx_data |= (rx_data_8 << (tmp * 8));
}
mspi->get_rx(rx_data, mspi);
}
- if (!(events & SPIE_NF)) {
+ if (!(events & SPIE_TNF)) {
int ret;
/* spin until TX is done */
- ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
- ®_base->event)) & SPIE_NF), 1000, 0);
+ ret = spin_event_timeout(((events = fsl_espi_read_reg(
+ mspi, ESPI_SPIE)) & SPIE_TNF), 1000, 0);
if (!ret) {
- dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
-
- /* Clear the SPIE bits */
- mpc8xxx_spi_write_reg(®_base->event, events);
+ dev_err(mspi->dev, "tired waiting for SPIE_TNF\n");
complete(&mspi->done);
return;
}
}
- /* Clear the events */
- mpc8xxx_spi_write_reg(®_base->event, events);
-
mspi->count -= 1;
if (mspi->count) {
u32 word = mspi->get_tx(mspi);
- mpc8xxx_spi_write_reg(®_base->transmit, word);
+ fsl_espi_write_reg(mspi, ESPI_SPITF, word);
} else {
complete(&mspi->done);
}
static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
{
struct mpc8xxx_spi *mspi = context_data;
- struct fsl_espi_reg *reg_base = mspi->reg_base;
- irqreturn_t ret = IRQ_NONE;
u32 events;
/* Get interrupt events(tx/rx) */
- events = mpc8xxx_spi_read_reg(®_base->event);
- if (events)
- ret = IRQ_HANDLED;
+ events = fsl_espi_read_reg(mspi, ESPI_SPIE);
+ if (!events)
+ return IRQ_NONE;
dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
fsl_espi_cpu_irq(mspi, events);
- return ret;
+ /* Clear the events */
+ fsl_espi_write_reg(mspi, ESPI_SPIE, events);
+
+ return IRQ_HANDLED;
}
#ifdef CONFIG_PM
{
struct spi_master *master = dev_get_drvdata(dev);
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
- struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
u32 regval;
- regval = mpc8xxx_spi_read_reg(®_base->mode);
+ regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE);
regval &= ~SPMODE_ENABLE;
- mpc8xxx_spi_write_reg(®_base->mode, regval);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
return 0;
}
{
struct spi_master *master = dev_get_drvdata(dev);
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
- struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
u32 regval;
- regval = mpc8xxx_spi_read_reg(®_base->mode);
+ regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE);
regval |= SPMODE_ENABLE;
- mpc8xxx_spi_write_reg(®_base->mode, regval);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
return 0;
}
return SPCOM_TRANLEN_MAX;
}
-static struct spi_master * fsl_espi_probe(struct device *dev,
- struct resource *mem, unsigned int irq)
+static int fsl_espi_probe(struct device *dev, struct resource *mem,
+ unsigned int irq)
{
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
struct spi_master *master;
struct mpc8xxx_spi *mpc8xxx_spi;
- struct fsl_espi_reg *reg_base;
struct device_node *nc;
const __be32 *prop;
u32 regval, csmode;
- int i, len, ret = 0;
+ int i, len, ret;
master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
- if (!master) {
- ret = -ENOMEM;
- goto err;
- }
+ if (!master)
+ return -ENOMEM;
dev_set_drvdata(dev, master);
goto err_probe;
}
- reg_base = mpc8xxx_spi->reg_base;
-
/* Register for SPI Interrupt */
ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
0, "fsl_espi", mpc8xxx_spi);
}
/* SPI controller initializations */
- mpc8xxx_spi_write_reg(®_base->mode, 0);
- mpc8xxx_spi_write_reg(®_base->mask, 0);
- mpc8xxx_spi_write_reg(®_base->command, 0);
- mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff);
/* Init eSPI CS mode register */
for_each_available_child_of_node(master->dev.of_node, nc) {
csmode &= ~(CSMODE_AFT(0xf));
csmode |= CSMODE_AFT(be32_to_cpup(prop));
}
- mpc8xxx_spi_write_reg(®_base->csmode[i], csmode);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i), csmode);
dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
}
/* Enable SPI interface */
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
- mpc8xxx_spi_write_reg(®_base->mode, regval);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
pm_runtime_use_autosuspend(dev);
if (ret < 0)
goto err_pm;
- dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
+ dev_info(dev, "at 0x%p (irq = %d)\n", mpc8xxx_spi->reg_base,
+ mpc8xxx_spi->irq);
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
- return master;
+ return 0;
err_pm:
pm_runtime_put_noidle(dev);
pm_runtime_set_suspended(dev);
err_probe:
spi_master_put(master);
-err:
- return ERR_PTR(ret);
+ return ret;
}
static int of_fsl_espi_get_chipselects(struct device *dev)
{
struct device *dev = &ofdev->dev;
struct device_node *np = ofdev->dev.of_node;
- struct spi_master *master;
struct resource mem;
unsigned int irq;
- int ret = -ENOMEM;
+ int ret;
ret = of_mpc8xxx_spi_probe(ofdev);
if (ret)
ret = of_fsl_espi_get_chipselects(dev);
if (ret)
- goto err;
+ return ret;
ret = of_address_to_resource(np, 0, &mem);
if (ret)
- goto err;
+ return ret;
irq = irq_of_parse_and_map(np, 0);
- if (!irq) {
- ret = -EINVAL;
- goto err;
- }
-
- master = fsl_espi_probe(dev, &mem, irq);
- if (IS_ERR(master)) {
- ret = PTR_ERR(master);
- goto err;
- }
-
- return 0;
+ if (!irq)
+ return -EINVAL;
-err:
- return ret;
+ return fsl_espi_probe(dev, &mem, irq);
}
static int of_fsl_espi_remove(struct platform_device *dev)
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
struct spi_master *master = dev_get_drvdata(dev);
struct mpc8xxx_spi *mpc8xxx_spi;
- struct fsl_espi_reg *reg_base;
u32 regval;
int i, ret;
mpc8xxx_spi = spi_master_get_devdata(master);
- reg_base = mpc8xxx_spi->reg_base;
/* SPI controller initializations */
- mpc8xxx_spi_write_reg(®_base->mode, 0);
- mpc8xxx_spi_write_reg(®_base->mask, 0);
- mpc8xxx_spi_write_reg(®_base->command, 0);
- mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff);
/* Init eSPI CS mode register */
for (i = 0; i < pdata->max_chipselect; i++)
- mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i),
+ CSMODE_INIT_VAL);
/* Enable SPI interface */
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
- mpc8xxx_spi_write_reg(®_base->mode, regval);
+ fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
ret = pm_runtime_force_resume(dev);
if (ret < 0)
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