Merge tag 'iio-for-4.7a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio...

[cascardo/linux.git] / drivers / staging / iio / adc / ad7192.c

diff --git a/drivers/staging/iio/adc/ad7192.c b/drivers/staging/iio/adc/ad7192.c
index 15d965c..1cf6b79 100644 (file)
--- a/drivers/staging/iio/adc/ad7192.c
+++ b/drivers/staging/iio/adc/ad7192.c
@@ -35,10 +35,10 @@
 #define AD7192_REG_DATA                3 /* Data Register           (RO, 24/32-bit) */
 #define AD7192_REG_ID          4 /* ID Register             (RO, 8-bit) */
 #define AD7192_REG_GPOCON      5 /* GPOCON Register         (RO, 8-bit) */
-#define AD7192_REG_OFFSET      6 /* Offset Register         (RW, 16-bit
-                                  * (AD7792)/24-bit (AD7192)) */
-#define AD7192_REG_FULLSALE    7 /* Full-Scale Register
-                                  * (RW, 16-bit (AD7792)/24-bit (AD7192)) */
+#define AD7192_REG_OFFSET      6 /* Offset Register         (RW, 16-bit */
+                                 /* (AD7792)/24-bit (AD7192)) */
+#define AD7192_REG_FULLSALE    7 /* Full-Scale Register */
+                                 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
 
 /* Communications Register Bit Designations (AD7192_REG_COMM) */
 #define AD7192_COMM_WEN                BIT(7) /* Write Enable */
@@ -80,13 +80,13 @@
 #define AD7192_MODE_CAL_SYS_FULL       7 /* System Full-Scale Calibration */
 
 /* Mode Register: AD7192_MODE_CLKSRC options */
-#define AD7192_CLK_EXT_MCLK1_2         0 /* External 4.92 MHz Clock connected
-                                          * from MCLK1 to MCLK2 */
+#define AD7192_CLK_EXT_MCLK1_2         0 /* External 4.92 MHz Clock connected*/
+                                         /* from MCLK1 to MCLK2 */
 #define AD7192_CLK_EXT_MCLK2           1 /* External Clock applied to MCLK2 */
-#define AD7192_CLK_INT                 2 /* Internal 4.92 MHz Clock not
-                                          * available at the MCLK2 pin */
-#define AD7192_CLK_INT_CO              3 /* Internal 4.92 MHz Clock available
-                                          * at the MCLK2 pin */
+#define AD7192_CLK_INT                 2 /* Internal 4.92 MHz Clock not */
+                                         /* available at the MCLK2 pin */
+#define AD7192_CLK_INT_CO              3 /* Internal 4.92 MHz Clock available*/
+                                         /* at the MCLK2 pin */
 
 /* Configuration Register Bit Designations (AD7192_REG_CONF) */