X-Git-Url: http://git.cascardo.info/?p=cascardo%2Flinux.git;a=blobdiff_plain;f=arch%2Fpowerpc%2Fkernel%2Fvector.S;fp=arch%2Fpowerpc%2Fkernel%2Fvector.S;h=0c123f3406cd0b19fc9bd8f08f6b6aeecd7235da;hp=388ec6477fc4400eace2fc9fc80fecb2e23b058f;hb=84d69848c97faab0c25aa2667b273404d2e2a64a;hpb=590abbdd273304b55824bcb9ea91840ea375575d

diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index 388ec6477fc4..0c123f3406cd 100644
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -8,31 +8,6 @@
 #include <asm/ptrace.h>
 #include <asm/export.h>
 
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-/* void do_load_up_transact_altivec(struct thread_struct *thread)
- *
- * This is similar to load_up_altivec but for the transactional version of the
- * vector regs.  It doesn't mess with the task MSR or valid flags.
- * Furthermore, VEC laziness is not supported with TM currently.
- */
-_GLOBAL(do_load_up_transact_altivec)
-	mfmsr	r6
-	oris	r5,r6,MSR_VEC@h
-	MTMSRD(r5)
-	isync
-
-	li	r4,1
-	stw	r4,THREAD_USED_VR(r3)
-
-	li	r10,THREAD_TRANSACT_VRSTATE+VRSTATE_VSCR
-	lvx	v0,r10,r3
-	mtvscr	v0
-	addi	r10,r3,THREAD_TRANSACT_VRSTATE
-	REST_32VRS(0,r4,r10)
-
-	blr
-#endif
-
 /*
  * Load state from memory into VMX registers including VSCR.
  * Assumes the caller has enabled VMX in the MSR.