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(parent: c1a3aca) | patch
usb: dwc3: exynos: Add provision for suspend clock
authorVivek Gautam <gautam.vivek@samsung.com>
Fri, 21 Nov 2014 13:35:46 +0000 (19:05 +0530)
committerFelipe Balbi <balbi@ti.com>
Fri, 21 Nov 2014 15:06:43 +0000 (09:06 -0600)
commit72d996fc7a01c2e4d581a15db7d001e2799ffb29
treebefa43b8232d147fba1703864ce2842ad729695etree | snapshot
parentc1a3acaadde7eb260f4fd4ec87cb87d3ffeed979commit | diff
usb: dwc3: exynos: Add provision for suspend clock

DWC3 controller on Exynos SoC series have separate control for
suspend clock which replaces pipe3_rx_pclk as clock source to
a small part of DWC3 core that operates when SS PHY is in its
lowest power state (P3) in states SS.disabled and U3.

Suggested-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
drivers/usb/dwc3/dwc3-exynos.c diff | blob | history
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