drm/i915: Handle PipeC fused off on IVB/HSW/BDW
authorGabriel Feceoru <gabriel.feceoru@intel.com>
Fri, 22 Jan 2016 11:28:45 +0000 (13:28 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 10 Feb 2016 07:29:34 +0000 (08:29 +0100)
commit8c448cadd4dd1bb3a8f34a93eaceb464d6e7a1db
treea24fb7cb9f7c5f48b8c5bf3f68c75dbcc501474c
parentda3b891b0fb88605bb2d16adaf1ef2a1f16403ba
drm/i915: Handle PipeC fused off on IVB/HSW/BDW

Some Gen7/8 production parts may have the Display Pipe C fused off.
In this case, the display hardware will prevent the enable bit in
PIPE_CONF register (for Pipe C) from being set to 1.

Fixed by adjusting pipe_count to reflect this.

v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
    on ivybridge (Ville)
v3: Remove unnecessary MMIO read, correct the description (Damien)
v4: Be more specific in description (Patrick)

Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1453462125-21519-1-git-send-email-gabriel.feceoru@intel.com
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_reg.h