ARM: mvebu: don't set the PL310 in I/O coherency mode when I/O coherency is disabled
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Wed, 28 Jan 2015 11:55:45 +0000 (12:55 +0100)
committerAndrew Lunn <andrew@lunn.ch>
Wed, 28 Jan 2015 17:23:56 +0000 (11:23 -0600)
commitdcad68876c21bac709b01eda24e39d4410dc36a8
treebed81a76c1066fd7a9f1f68b30baa7be61d570e5
parent38bdf45f4aa5cb6186d50a29e6cbbd9d486a1519
ARM: mvebu: don't set the PL310 in I/O coherency mode when I/O coherency is disabled

Since commit f2c3c67f00 (merge commit that adds commit "ARM: mvebu:
completely disable hardware I/O coherency"), we disable I/O coherency
on Armada EBU platforms.

However, we continue to initialize the coherency fabric, because this
coherency fabric is needed on Armada XP for inter-CPU
coherency. Unfortunately, due to this, we also continued to execute
the coherency fabric initialization code for Armada 375/38x, which
switched the PL310 into I/O coherent mode. This has the effect of
disabling the outer cache sync operation: this is needed when I/O
coherency is enabled to work around a PCIe/L2 deadlock. But obviously,
when I/O coherency is disabled, having the outer cache sync operation
is crucial.

Therefore, this commit fixes the armada_375_380_coherency_init() so
that the PL310 is switched to I/O coherent mode only if I/O coherency
is enabled.

Without this fix, all devices using DMA are broken on Armada 375/38x.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Cc: <stable@vger.kernel.org> # v3.8+
arch/arm/mach-mvebu/coherency.c