Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

Pull crypto updates from Herbert Xu:
 "Here is the crypto update for 4.9:

  API:
   - The crypto engine code now supports hashes.

  Algorithms:
   - Allow keys >= 2048 bits in FIPS mode for RSA.

  Drivers:
   - Memory overwrite fix for vmx ghash.
   - Add support for building ARM sha1-neon in Thumb2 mode.
   - Reenable ARM ghash-ce code by adding import/export.
   - Reenable img-hash by adding import/export.
   - Add support for multiple cores in omap-aes.
   - Add little-endian support for sha1-powerpc.
   - Add Cavium HWRNG driver for ThunderX SoC"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (137 commits)
  crypto: caam - treat SGT address pointer as u64
  crypto: ccp - Make syslog errors human-readable
  crypto: ccp - clean up data structure
  crypto: vmx - Ensure ghash-generic is enabled
  crypto: testmgr - add guard to dst buffer for ahash_export
  crypto: caam - Unmap region obtained by of_iomap
  crypto: sha1-powerpc - little-endian support
  crypto: gcm - Fix IV buffer size in crypto_gcm_setkey
  crypto: vmx - Fix memory corruption caused by p8_ghash
  crypto: ghash-generic - move common definitions to a new header file
  crypto: caam - fix sg dump
  hwrng: omap - Only fail if pm_runtime_get_sync returns < 0
  crypto: omap-sham - shrink the internal buffer size
  crypto: omap-sham - add support for export/import
  crypto: omap-sham - convert driver logic to use sgs for data xmit
  crypto: omap-sham - change the DMA threshold value to a define
  crypto: omap-sham - add support functions for sg based data handling
  crypto: omap-sham - rename sgl to sgl_tmp for deprecation
  crypto: omap-sham - align algorithms on word offset
  crypto: omap-sham - add context export/import stubs
  ...

diff --combined drivers/crypto/Kconfig
index 9b035b7,19ee6ee..4d2b81f
--- 1/drivers/crypto/Kconfig
--- 2/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@@ -318,6 -318,9 +318,9 @@@ config CRYPTO_DEV_OMAP_AE
        select CRYPTO_AES
        select CRYPTO_BLKCIPHER
        select CRYPTO_ENGINE
+       select CRYPTO_CBC
+       select CRYPTO_ECB
+       select CRYPTO_CTR
        help
          OMAP processors have AES module accelerator. Select this if you
          want to use the OMAP module for AES algorithms.
@@@ -550,6 -553,4 +553,6 @@@ config CRYPTO_DEV_ROCKCHI
          This driver interfaces with the hardware crypto accelerator.
          Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
  
 +source "drivers/crypto/chelsio/Kconfig"
 +
  endif # CRYPTO_HW

diff --combined drivers/pci/quirks.c
index cffc1c0,7060823..c232729
--- 1/drivers/pci/quirks.c
--- 2/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@@ -834,6 -834,17 +834,17 @@@ static void quirk_amd_ioapic(struct pci
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,    PCI_DEVICE_ID_AMD_VIPER_7410,   quirk_amd_ioapic);
  #endif /* CONFIG_X86_IO_APIC */
  
+ #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
+ 
+ static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
+ {
+       /* Fix for improper SRIOV configuration on Cavium cn88xx  RNM device */
+       if (dev->subsystem_device == 0xa118)
+               dev->sriov->link = dev->devfn;
+ }
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
+ #endif
+ 
  /*
   * Some settings of MMRBC can lead to data corruption so block changes.
   * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
@@@ -3198,7 -3209,6 +3209,7 @@@ static void quirk_no_bus_reset(struct p
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
  
  static void quirk_no_pm_reset(struct pci_dev *dev)
  {
@@@ -3328,9 -3338,9 +3339,9 @@@ static void quirk_apple_wait_for_thunde
        if (nhi->vendor != PCI_VENDOR_ID_INTEL
                    || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
                        nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
 +                      nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
                        nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
 -                  || nhi->subsystem_vendor != 0x2222
 -                  || nhi->subsystem_device != 0x1111)
 +                  || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
                goto out;
        dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
        device_pm_wait_for_dev(&dev->dev, &nhi->dev);
@@@ -3344,9 -3354,6 +3355,9 @@@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VEND
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
                               PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
                               quirk_apple_wait_for_thunderbolt);
 +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
 +                             PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
 +                             quirk_apple_wait_for_thunderbolt);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
                               PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
                               quirk_apple_wait_for_thunderbolt);
@@@ -4432,20 -4439,3 +4443,20 @@@ static void quirk_intel_qat_vf_cap(stru
        }
  }
  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
 +
 +/*
 + * VMD-enabled root ports will change the source ID for all messages
 + * to the VMD device. Rather than doing device matching with the source
 + * ID, the AER driver should traverse the child device tree, reading
 + * AER registers to find the faulting device.
 + */
 +static void quirk_no_aersid(struct pci_dev *pdev)
 +{
 +      /* VMD Domain */
 +      if (pdev->bus->sysdata && pci_domain_nr(pdev->bus) >= 0x10000)
 +              pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID;
 +}
 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid);
 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);