From 53e5bff16f82ea4326102e668e0e91b3ab4129ba Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 10 Oct 2016 07:50:07 -0500 Subject: [PATCH] PCI: exynos: Uninline register accessors The register accessors are not performance critical and are small enough that the compiler can inline them itself if it makes sense. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-exynos.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index e633817aeaf6..8e841f8340d5 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -102,32 +102,32 @@ struct exynos_pcie { #define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7) #define PCIE_PHY_TRSV3_LVCC 0x31c -static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg) +static void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg) { writel(val, pcie->elbi_base + reg); } -static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg) +static u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg) { return readl(pcie->elbi_base + reg); } -static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg) +static void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg) { writel(val, pcie->phy_base + reg); } -static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg) +static u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg) { return readl(pcie->phy_base + reg); } -static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg) +static void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg) { writel(val, pcie->block_base + reg); } -static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg) +static u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg) { return readl(pcie->block_base + reg); } @@ -427,7 +427,7 @@ static void exynos_pcie_enable_interrupts(struct pcie_port *pp) exynos_pcie_msi_init(pp); } -static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg) +static u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg) { u32 val; @@ -437,7 +437,7 @@ static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg) return val; } -static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) +static void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) { exynos_pcie_sideband_dbi_w_mode(pp, true); writel(val, pp->dbi_base + reg); -- 2.20.1