drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include "xhci.h"
  30 #include "xhci-trace.h"
  31
  32 /*
  33  * Allocates a generic ring segment from the ring pool, sets the dma address,
  34  * initializes the segment to zero, and sets the private next pointer to NULL.
  35  *
  36  * Section 4.11.1.1:
  37  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  38  */
  39 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
  40                                         unsigned int cycle_state, gfp_t flags)
  41 {
  42         struct xhci_segment *seg;
  43         dma_addr_t      dma;
  44         int             i;
  45
  46         seg = kzalloc(sizeof *seg, flags);
  47         if (!seg)
  48                 return NULL;
  49
  50         seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma);
  51         if (!seg->trbs) {
  52                 kfree(seg);
  53                 return NULL;
  54         }
  55
  56         /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
  57         if (cycle_state == 0) {
  58                 for (i = 0; i < TRBS_PER_SEGMENT; i++)
  59                         seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE);
  60         }
  61         seg->dma = dma;
  62         seg->next = NULL;
  63
  64         return seg;
  65 }
  66
  67 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  68 {
  69         if (seg->trbs) {
  70                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  71                 seg->trbs = NULL;
  72         }
  73         kfree(seg);
  74 }
  75
  76 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
  77                                 struct xhci_segment *first)
  78 {
  79         struct xhci_segment *seg;
  80
  81         seg = first->next;
  82         while (seg != first) {
  83                 struct xhci_segment *next = seg->next;
  84                 xhci_segment_free(xhci, seg);
  85                 seg = next;
  86         }
  87         xhci_segment_free(xhci, first);
  88 }
  89
  90 /*
  91  * Make the prev segment point to the next segment.
  92  *
  93  * Change the last TRB in the prev segment to be a Link TRB which points to the
  94  * DMA address of the next segment.  The caller needs to set any Link TRB
  95  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  96  */
  97 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  98                 struct xhci_segment *next, enum xhci_ring_type type)
  99 {
 100         u32 val;
 101
 102         if (!prev || !next)
 103                 return;
 104         prev->next = next;
 105         if (type != TYPE_EVENT) {
 106                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
 107                         cpu_to_le64(next->dma);
 108
 109                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
 110                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
 111                 val &= ~TRB_TYPE_BITMASK;
 112                 val |= TRB_TYPE(TRB_LINK);
 113                 /* Always set the chain bit with 0.95 hardware */
 114                 /* Set chain bit for isoc rings on AMD 0.96 host */
 115                 if (xhci_link_trb_quirk(xhci) ||
 116                                 (type == TYPE_ISOC &&
 117                                  (xhci->quirks & XHCI_AMD_0x96_HOST)))
 118                         val |= TRB_CHAIN;
 119                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
 120         }
 121 }
 122
 123 /*
 124  * Link the ring to the new segments.
 125  * Set Toggle Cycle for the new ring if needed.
 126  */
 127 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
 128                 struct xhci_segment *first, struct xhci_segment *last,
 129                 unsigned int num_segs)
 130 {
 131         struct xhci_segment *next;
 132
 133         if (!ring || !first || !last)
 134                 return;
 135
 136         next = ring->enq_seg->next;
 137         xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
 138         xhci_link_segments(xhci, last, next, ring->type);
 139         ring->num_segs += num_segs;
 140         ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
 141
 142         if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
 143                 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
 144                         &= ~cpu_to_le32(LINK_TOGGLE);
 145                 last->trbs[TRBS_PER_SEGMENT-1].link.control
 146                         |= cpu_to_le32(LINK_TOGGLE);
 147                 ring->last_seg = last;
 148         }
 149 }
 150
 151 /*
 152  * We need a radix tree for mapping physical addresses of TRBs to which stream
 153  * ID they belong to.  We need to do this because the host controller won't tell
 154  * us which stream ring the TRB came from.  We could store the stream ID in an
 155  * event data TRB, but that doesn't help us for the cancellation case, since the
 156  * endpoint may stop before it reaches that event data TRB.
 157  *
 158  * The radix tree maps the upper portion of the TRB DMA address to a ring
 159  * segment that has the same upper portion of DMA addresses.  For example, say I
 160  * have segments of size 1KB, that are always 1KB aligned.  A segment may
 161  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 162  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 163  * pass the radix tree a key to get the right stream ID:
 164  *
 165  *      0x10c90fff >> 10 = 0x43243
 166  *      0x10c912c0 >> 10 = 0x43244
 167  *      0x10c91400 >> 10 = 0x43245
 168  *
 169  * Obviously, only those TRBs with DMA addresses that are within the segment
 170  * will make the radix tree return the stream ID for that ring.
 171  *
 172  * Caveats for the radix tree:
 173  *
 174  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 175  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 176  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 177  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 178  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 179  * extended systems (where the DMA address can be bigger than 32-bits),
 180  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 181  */
 182 static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map,
 183                 struct xhci_ring *ring,
 184                 struct xhci_segment *seg,
 185                 gfp_t mem_flags)
 186 {
 187         unsigned long key;
 188         int ret;
 189
 190         key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
 191         /* Skip any segments that were already added. */
 192         if (radix_tree_lookup(trb_address_map, key))
 193                 return 0;
 194
 195         ret = radix_tree_maybe_preload(mem_flags);
 196         if (ret)
 197                 return ret;
 198         ret = radix_tree_insert(trb_address_map,
 199                         key, ring);
 200         radix_tree_preload_end();
 201         return ret;
 202 }
 203
 204 static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map,
 205                 struct xhci_segment *seg)
 206 {
 207         unsigned long key;
 208
 209         key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
 210         if (radix_tree_lookup(trb_address_map, key))
 211                 radix_tree_delete(trb_address_map, key);
 212 }
 213
 214 static int xhci_update_stream_segment_mapping(
 215                 struct radix_tree_root *trb_address_map,
 216                 struct xhci_ring *ring,
 217                 struct xhci_segment *first_seg,
 218                 struct xhci_segment *last_seg,
 219                 gfp_t mem_flags)
 220 {
 221         struct xhci_segment *seg;
 222         struct xhci_segment *failed_seg;
 223         int ret;
 224
 225         if (WARN_ON_ONCE(trb_address_map == NULL))
 226                 return 0;
 227
 228         seg = first_seg;
 229         do {
 230                 ret = xhci_insert_segment_mapping(trb_address_map,
 231                                 ring, seg, mem_flags);
 232                 if (ret)
 233                         goto remove_streams;
 234                 if (seg == last_seg)
 235                         return 0;
 236                 seg = seg->next;
 237         } while (seg != first_seg);
 238
 239         return 0;
 240
 241 remove_streams:
 242         failed_seg = seg;
 243         seg = first_seg;
 244         do {
 245                 xhci_remove_segment_mapping(trb_address_map, seg);
 246                 if (seg == failed_seg)
 247                         return ret;
 248                 seg = seg->next;
 249         } while (seg != first_seg);
 250
 251         return ret;
 252 }
 253
 254 static void xhci_remove_stream_mapping(struct xhci_ring *ring)
 255 {
 256         struct xhci_segment *seg;
 257
 258         if (WARN_ON_ONCE(ring->trb_address_map == NULL))
 259                 return;
 260
 261         seg = ring->first_seg;
 262         do {
 263                 xhci_remove_segment_mapping(ring->trb_address_map, seg);
 264                 seg = seg->next;
 265         } while (seg != ring->first_seg);
 266 }
 267
 268 static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags)
 269 {
 270         return xhci_update_stream_segment_mapping(ring->trb_address_map, ring,
 271                         ring->first_seg, ring->last_seg, mem_flags);
 272 }
 273
 274 /* XXX: Do we need the hcd structure in all these functions? */
 275 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 276 {
 277         if (!ring)
 278                 return;
 279
 280         if (ring->first_seg) {
 281                 if (ring->type == TYPE_STREAM)
 282                         xhci_remove_stream_mapping(ring);
 283                 xhci_free_segments_for_ring(xhci, ring->first_seg);
 284         }
 285
 286         kfree(ring);
 287 }
 288
 289 static void xhci_initialize_ring_info(struct xhci_ring *ring,
 290                                         unsigned int cycle_state)
 291 {
 292         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 293         ring->enqueue = ring->first_seg->trbs;
 294         ring->enq_seg = ring->first_seg;
 295         ring->dequeue = ring->enqueue;
 296         ring->deq_seg = ring->first_seg;
 297         /* The ring is initialized to 0. The producer must write 1 to the cycle
 298          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 299          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 300          *
 301          * New rings are initialized with cycle state equal to 1; if we are
 302          * handling ring expansion, set the cycle state equal to the old ring.
 303          */
 304         ring->cycle_state = cycle_state;
 305         /* Not necessary for new rings, but needed for re-initialized rings */
 306         ring->enq_updates = 0;
 307         ring->deq_updates = 0;
 308
 309         /*
 310          * Each segment has a link TRB, and leave an extra TRB for SW
 311          * accounting purpose
 312          */
 313         ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
 314 }
 315
 316 /* Allocate segments and link them for a ring */
 317 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
 318                 struct xhci_segment **first, struct xhci_segment **last,
 319                 unsigned int num_segs, unsigned int cycle_state,
 320                 enum xhci_ring_type type, gfp_t flags)
 321 {
 322         struct xhci_segment *prev;
 323
 324         prev = xhci_segment_alloc(xhci, cycle_state, flags);
 325         if (!prev)
 326                 return -ENOMEM;
 327         num_segs--;
 328
 329         *first = prev;
 330         while (num_segs > 0) {
 331                 struct xhci_segment     *next;
 332
 333                 next = xhci_segment_alloc(xhci, cycle_state, flags);
 334                 if (!next) {
 335                         prev = *first;
 336                         while (prev) {
 337                                 next = prev->next;
 338                                 xhci_segment_free(xhci, prev);
 339                                 prev = next;
 340                         }
 341                         return -ENOMEM;
 342                 }
 343                 xhci_link_segments(xhci, prev, next, type);
 344
 345                 prev = next;
 346                 num_segs--;
 347         }
 348         xhci_link_segments(xhci, prev, *first, type);
 349         *last = prev;
 350
 351         return 0;
 352 }
 353
 354 /**
 355  * Create a new ring with zero or more segments.
 356  *
 357  * Link each segment together into a ring.
 358  * Set the end flag and the cycle toggle bit on the last segment.
 359  * See section 4.9.1 and figures 15 and 16.
 360  */
 361 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 362                 unsigned int num_segs, unsigned int cycle_state,
 363                 enum xhci_ring_type type, gfp_t flags)
 364 {
 365         struct xhci_ring        *ring;
 366         int ret;
 367
 368         ring = kzalloc(sizeof *(ring), flags);
 369         if (!ring)
 370                 return NULL;
 371
 372         ring->num_segs = num_segs;
 373         INIT_LIST_HEAD(&ring->td_list);
 374         ring->type = type;
 375         if (num_segs == 0)
 376                 return ring;
 377
 378         ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
 379                         &ring->last_seg, num_segs, cycle_state, type, flags);
 380         if (ret)
 381                 goto fail;
 382
 383         /* Only event ring does not use link TRB */
 384         if (type != TYPE_EVENT) {
 385                 /* See section 4.9.2.1 and 6.4.4.1 */
 386                 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
 387                         cpu_to_le32(LINK_TOGGLE);
 388         }
 389         xhci_initialize_ring_info(ring, cycle_state);
 390         return ring;
 391
 392 fail:
 393         kfree(ring);
 394         return NULL;
 395 }
 396
 397 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 398                 struct xhci_virt_device *virt_dev,
 399                 unsigned int ep_index)
 400 {
 401         int rings_cached;
 402
 403         rings_cached = virt_dev->num_rings_cached;
 404         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 405                 virt_dev->ring_cache[rings_cached] =
 406                         virt_dev->eps[ep_index].ring;
 407                 virt_dev->num_rings_cached++;
 408                 xhci_dbg(xhci, "Cached old ring, "
 409                                 "%d ring%s cached\n",
 410                                 virt_dev->num_rings_cached,
 411                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
 412         } else {
 413                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 414                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 415                                 "freeing ring\n",
 416                                 virt_dev->num_rings_cached);
 417         }
 418         virt_dev->eps[ep_index].ring = NULL;
 419 }
 420
 421 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 422  * pointers to the beginning of the ring.
 423  */
 424 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 425                         struct xhci_ring *ring, unsigned int cycle_state,
 426                         enum xhci_ring_type type)
 427 {
 428         struct xhci_segment     *seg = ring->first_seg;
 429         int i;
 430
 431         do {
 432                 memset(seg->trbs, 0,
 433                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 434                 if (cycle_state == 0) {
 435                         for (i = 0; i < TRBS_PER_SEGMENT; i++)
 436                                 seg->trbs[i].link.control |=
 437                                         cpu_to_le32(TRB_CYCLE);
 438                 }
 439                 /* All endpoint rings have link TRBs */
 440                 xhci_link_segments(xhci, seg, seg->next, type);
 441                 seg = seg->next;
 442         } while (seg != ring->first_seg);
 443         ring->type = type;
 444         xhci_initialize_ring_info(ring, cycle_state);
 445         /* td list should be empty since all URBs have been cancelled,
 446          * but just in case...
 447          */
 448         INIT_LIST_HEAD(&ring->td_list);
 449 }
 450
 451 /*
 452  * Expand an existing ring.
 453  * Look for a cached ring or allocate a new ring which has same segment numbers
 454  * and link the two rings.
 455  */
 456 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
 457                                 unsigned int num_trbs, gfp_t flags)
 458 {
 459         struct xhci_segment     *first;
 460         struct xhci_segment     *last;
 461         unsigned int            num_segs;
 462         unsigned int            num_segs_needed;
 463         int                     ret;
 464
 465         num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
 466                                 (TRBS_PER_SEGMENT - 1);
 467
 468         /* Allocate number of segments we needed, or double the ring size */
 469         num_segs = ring->num_segs > num_segs_needed ?
 470                         ring->num_segs : num_segs_needed;
 471
 472         ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
 473                         num_segs, ring->cycle_state, ring->type, flags);
 474         if (ret)
 475                 return -ENOMEM;
 476
 477         if (ring->type == TYPE_STREAM)
 478                 ret = xhci_update_stream_segment_mapping(ring->trb_address_map,
 479                                                 ring, first, last, flags);
 480         if (ret) {
 481                 struct xhci_segment *next;
 482                 do {
 483                         next = first->next;
 484                         xhci_segment_free(xhci, first);
 485                         if (first == last)
 486                                 break;
 487                         first = next;
 488                 } while (true);
 489                 return ret;
 490         }
 491
 492         xhci_link_rings(xhci, ring, first, last, num_segs);
 493         xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
 494                         "ring expansion succeed, now has %d segments",
 495                         ring->num_segs);
 496
 497         return 0;
 498 }
 499
 500 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 501
 502 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 503                                                     int type, gfp_t flags)
 504 {
 505         struct xhci_container_ctx *ctx;
 506
 507         if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
 508                 return NULL;
 509
 510         ctx = kzalloc(sizeof(*ctx), flags);
 511         if (!ctx)
 512                 return NULL;
 513
 514         ctx->type = type;
 515         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 516         if (type == XHCI_CTX_TYPE_INPUT)
 517                 ctx->size += CTX_SIZE(xhci->hcc_params);
 518
 519         ctx->bytes = dma_pool_zalloc(xhci->device_pool, flags, &ctx->dma);
 520         if (!ctx->bytes) {
 521                 kfree(ctx);
 522                 return NULL;
 523         }
 524         return ctx;
 525 }
 526
 527 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 528                              struct xhci_container_ctx *ctx)
 529 {
 530         if (!ctx)
 531                 return;
 532         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 533         kfree(ctx);
 534 }
 535
 536 struct xhci_input_control_ctx *xhci_get_input_control_ctx(
 537                                               struct xhci_container_ctx *ctx)
 538 {
 539         if (ctx->type != XHCI_CTX_TYPE_INPUT)
 540                 return NULL;
 541
 542         return (struct xhci_input_control_ctx *)ctx->bytes;
 543 }
 544
 545 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 546                                         struct xhci_container_ctx *ctx)
 547 {
 548         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 549                 return (struct xhci_slot_ctx *)ctx->bytes;
 550
 551         return (struct xhci_slot_ctx *)
 552                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 553 }
 554
 555 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 556                                     struct xhci_container_ctx *ctx,
 557                                     unsigned int ep_index)
 558 {
 559         /* increment ep index by offset of start of ep ctx array */
 560         ep_index++;
 561         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 562                 ep_index++;
 563
 564         return (struct xhci_ep_ctx *)
 565                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 566 }
 567
 568
 569 /***************** Streams structures manipulation *************************/
 570
 571 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 572                 unsigned int num_stream_ctxs,
 573                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 574 {
 575         struct device *dev = xhci_to_hcd(xhci)->self.controller;
 576         size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
 577
 578         if (size > MEDIUM_STREAM_ARRAY_SIZE)
 579                 dma_free_coherent(dev, size,
 580                                 stream_ctx, dma);
 581         else if (size <= SMALL_STREAM_ARRAY_SIZE)
 582                 return dma_pool_free(xhci->small_streams_pool,
 583                                 stream_ctx, dma);
 584         else
 585                 return dma_pool_free(xhci->medium_streams_pool,
 586                                 stream_ctx, dma);
 587 }
 588
 589 /*
 590  * The stream context array for each endpoint with bulk streams enabled can
 591  * vary in size, based on:
 592  *  - how many streams the endpoint supports,
 593  *  - the maximum primary stream array size the host controller supports,
 594  *  - and how many streams the device driver asks for.
 595  *
 596  * The stream context array must be a power of 2, and can be as small as
 597  * 64 bytes or as large as 1MB.
 598  */
 599 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 600                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 601                 gfp_t mem_flags)
 602 {
 603         struct device *dev = xhci_to_hcd(xhci)->self.controller;
 604         size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
 605
 606         if (size > MEDIUM_STREAM_ARRAY_SIZE)
 607                 return dma_alloc_coherent(dev, size,
 608                                 dma, mem_flags);
 609         else if (size <= SMALL_STREAM_ARRAY_SIZE)
 610                 return dma_pool_alloc(xhci->small_streams_pool,
 611                                 mem_flags, dma);
 612         else
 613                 return dma_pool_alloc(xhci->medium_streams_pool,
 614                                 mem_flags, dma);
 615 }
 616
 617 struct xhci_ring *xhci_dma_to_transfer_ring(
 618                 struct xhci_virt_ep *ep,
 619                 u64 address)
 620 {
 621         if (ep->ep_state & EP_HAS_STREAMS)
 622                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 623                                 address >> TRB_SEGMENT_SHIFT);
 624         return ep->ring;
 625 }
 626
 627 struct xhci_ring *xhci_stream_id_to_ring(
 628                 struct xhci_virt_device *dev,
 629                 unsigned int ep_index,
 630                 unsigned int stream_id)
 631 {
 632         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 633
 634         if (stream_id == 0)
 635                 return ep->ring;
 636         if (!ep->stream_info)
 637                 return NULL;
 638
 639         if (stream_id > ep->stream_info->num_streams)
 640                 return NULL;
 641         return ep->stream_info->stream_rings[stream_id];
 642 }
 643
 644 /*
 645  * Change an endpoint's internal structure so it supports stream IDs.  The
 646  * number of requested streams includes stream 0, which cannot be used by device
 647  * drivers.
 648  *
 649  * The number of stream contexts in the stream context array may be bigger than
 650  * the number of streams the driver wants to use.  This is because the number of
 651  * stream context array entries must be a power of two.
 652  */
 653 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 654                 unsigned int num_stream_ctxs,
 655                 unsigned int num_streams, gfp_t mem_flags)
 656 {
 657         struct xhci_stream_info *stream_info;
 658         u32 cur_stream;
 659         struct xhci_ring *cur_ring;
 660         u64 addr;
 661         int ret;
 662
 663         xhci_dbg(xhci, "Allocating %u streams and %u "
 664                         "stream context array entries.\n",
 665                         num_streams, num_stream_ctxs);
 666         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 667                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 668                 return NULL;
 669         }
 670         xhci->cmd_ring_reserved_trbs++;
 671
 672         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 673         if (!stream_info)
 674                 goto cleanup_trbs;
 675
 676         stream_info->num_streams = num_streams;
 677         stream_info->num_stream_ctxs = num_stream_ctxs;
 678
 679         /* Initialize the array of virtual pointers to stream rings. */
 680         stream_info->stream_rings = kzalloc(
 681                         sizeof(struct xhci_ring *)*num_streams,
 682                         mem_flags);
 683         if (!stream_info->stream_rings)
 684                 goto cleanup_info;
 685
 686         /* Initialize the array of DMA addresses for stream rings for the HW. */
 687         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 688                         num_stream_ctxs, &stream_info->ctx_array_dma,
 689                         mem_flags);
 690         if (!stream_info->stream_ctx_array)
 691                 goto cleanup_ctx;
 692         memset(stream_info->stream_ctx_array, 0,
 693                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 694
 695         /* Allocate everything needed to free the stream rings later */
 696         stream_info->free_streams_command =
 697                 xhci_alloc_command(xhci, true, true, mem_flags);
 698         if (!stream_info->free_streams_command)
 699                 goto cleanup_ctx;
 700
 701         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 702
 703         /* Allocate rings for all the streams that the driver will use,
 704          * and add their segment DMA addresses to the radix tree.
 705          * Stream 0 is reserved.
 706          */
 707         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 708                 stream_info->stream_rings[cur_stream] =
 709                         xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags);
 710                 cur_ring = stream_info->stream_rings[cur_stream];
 711                 if (!cur_ring)
 712                         goto cleanup_rings;
 713                 cur_ring->stream_id = cur_stream;
 714                 cur_ring->trb_address_map = &stream_info->trb_address_map;
 715                 /* Set deq ptr, cycle bit, and stream context type */
 716                 addr = cur_ring->first_seg->dma |
 717                         SCT_FOR_CTX(SCT_PRI_TR) |
 718                         cur_ring->cycle_state;
 719                 stream_info->stream_ctx_array[cur_stream].stream_ring =
 720                         cpu_to_le64(addr);
 721                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 722                                 cur_stream, (unsigned long long) addr);
 723
 724                 ret = xhci_update_stream_mapping(cur_ring, mem_flags);
 725                 if (ret) {
 726                         xhci_ring_free(xhci, cur_ring);
 727                         stream_info->stream_rings[cur_stream] = NULL;
 728                         goto cleanup_rings;
 729                 }
 730         }
 731         /* Leave the other unused stream ring pointers in the stream context
 732          * array initialized to zero.  This will cause the xHC to give us an
 733          * error if the device asks for a stream ID we don't have setup (if it
 734          * was any other way, the host controller would assume the ring is
 735          * "empty" and wait forever for data to be queued to that stream ID).
 736          */
 737
 738         return stream_info;
 739
 740 cleanup_rings:
 741         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 742                 cur_ring = stream_info->stream_rings[cur_stream];
 743                 if (cur_ring) {
 744                         xhci_ring_free(xhci, cur_ring);
 745                         stream_info->stream_rings[cur_stream] = NULL;
 746                 }
 747         }
 748         xhci_free_command(xhci, stream_info->free_streams_command);
 749 cleanup_ctx:
 750         kfree(stream_info->stream_rings);
 751 cleanup_info:
 752         kfree(stream_info);
 753 cleanup_trbs:
 754         xhci->cmd_ring_reserved_trbs--;
 755         return NULL;
 756 }
 757 /*
 758  * Sets the MaxPStreams field and the Linear Stream Array field.
 759  * Sets the dequeue pointer to the stream context array.
 760  */
 761 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 762                 struct xhci_ep_ctx *ep_ctx,
 763                 struct xhci_stream_info *stream_info)
 764 {
 765         u32 max_primary_streams;
 766         /* MaxPStreams is the number of stream context array entries, not the
 767          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 768          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 769          */
 770         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 771         xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
 772                         "Setting number of stream ctx array entries to %u",
 773                         1 << (max_primary_streams + 1));
 774         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 775         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 776                                        | EP_HAS_LSA);
 777         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 778 }
 779
 780 /*
 781  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 782  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 783  * not at the beginning of the ring).
 784  */
 785 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
 786                 struct xhci_virt_ep *ep)
 787 {
 788         dma_addr_t addr;
 789         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 790         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 791         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 792 }
 793
 794 /* Frees all stream contexts associated with the endpoint,
 795  *
 796  * Caller should fix the endpoint context streams fields.
 797  */
 798 void xhci_free_stream_info(struct xhci_hcd *xhci,
 799                 struct xhci_stream_info *stream_info)
 800 {
 801         int cur_stream;
 802         struct xhci_ring *cur_ring;
 803
 804         if (!stream_info)
 805                 return;
 806
 807         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 808                         cur_stream++) {
 809                 cur_ring = stream_info->stream_rings[cur_stream];
 810                 if (cur_ring) {
 811                         xhci_ring_free(xhci, cur_ring);
 812                         stream_info->stream_rings[cur_stream] = NULL;
 813                 }
 814         }
 815         xhci_free_command(xhci, stream_info->free_streams_command);
 816         xhci->cmd_ring_reserved_trbs--;
 817         if (stream_info->stream_ctx_array)
 818                 xhci_free_stream_ctx(xhci,
 819                                 stream_info->num_stream_ctxs,
 820                                 stream_info->stream_ctx_array,
 821                                 stream_info->ctx_array_dma);
 822
 823         kfree(stream_info->stream_rings);
 824         kfree(stream_info);
 825 }
 826
 827
 828 /***************** Device context manipulation *************************/
 829
 830 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 831                 struct xhci_virt_ep *ep)
 832 {
 833         setup_timer(&ep->stop_cmd_timer, xhci_stop_endpoint_command_watchdog,
 834                     (unsigned long)ep);
 835         ep->xhci = xhci;
 836 }
 837
 838 static void xhci_free_tt_info(struct xhci_hcd *xhci,
 839                 struct xhci_virt_device *virt_dev,
 840                 int slot_id)
 841 {
 842         struct list_head *tt_list_head;
 843         struct xhci_tt_bw_info *tt_info, *next;
 844         bool slot_found = false;
 845
 846         /* If the device never made it past the Set Address stage,
 847          * it may not have the real_port set correctly.
 848          */
 849         if (virt_dev->real_port == 0 ||
 850                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
 851                 xhci_dbg(xhci, "Bad real port.\n");
 852                 return;
 853         }
 854
 855         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
 856         list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
 857                 /* Multi-TT hubs will have more than one entry */
 858                 if (tt_info->slot_id == slot_id) {
 859                         slot_found = true;
 860                         list_del(&tt_info->tt_list);
 861                         kfree(tt_info);
 862                 } else if (slot_found) {
 863                         break;
 864                 }
 865         }
 866 }
 867
 868 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
 869                 struct xhci_virt_device *virt_dev,
 870                 struct usb_device *hdev,
 871                 struct usb_tt *tt, gfp_t mem_flags)
 872 {
 873         struct xhci_tt_bw_info          *tt_info;
 874         unsigned int                    num_ports;
 875         int                             i, j;
 876
 877         if (!tt->multi)
 878                 num_ports = 1;
 879         else
 880                 num_ports = hdev->maxchild;
 881
 882         for (i = 0; i < num_ports; i++, tt_info++) {
 883                 struct xhci_interval_bw_table *bw_table;
 884
 885                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
 886                 if (!tt_info)
 887                         goto free_tts;
 888                 INIT_LIST_HEAD(&tt_info->tt_list);
 889                 list_add(&tt_info->tt_list,
 890                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
 891                 tt_info->slot_id = virt_dev->udev->slot_id;
 892                 if (tt->multi)
 893                         tt_info->ttport = i+1;
 894                 bw_table = &tt_info->bw_table;
 895                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
 896                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
 897         }
 898         return 0;
 899
 900 free_tts:
 901         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
 902         return -ENOMEM;
 903 }
 904
 905
 906 /* All the xhci_tds in the ring's TD list should be freed at this point.
 907  * Should be called with xhci->lock held if there is any chance the TT lists
 908  * will be manipulated by the configure endpoint, allocate device, or update
 909  * hub functions while this function is removing the TT entries from the list.
 910  */
 911 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 912 {
 913         struct xhci_virt_device *dev;
 914         int i;
 915         int old_active_eps = 0;
 916
 917         /* Slot ID 0 is reserved */
 918         if (slot_id == 0 || !xhci->devs[slot_id])
 919                 return;
 920
 921         dev = xhci->devs[slot_id];
 922         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 923         if (!dev)
 924                 return;
 925
 926         if (dev->tt_info)
 927                 old_active_eps = dev->tt_info->active_eps;
 928
 929         for (i = 0; i < 31; ++i) {
 930                 if (dev->eps[i].ring)
 931                         xhci_ring_free(xhci, dev->eps[i].ring);
 932                 if (dev->eps[i].stream_info)
 933                         xhci_free_stream_info(xhci,
 934                                         dev->eps[i].stream_info);
 935                 /* Endpoints on the TT/root port lists should have been removed
 936                  * when usb_disable_device() was called for the device.
 937                  * We can't drop them anyway, because the udev might have gone
 938                  * away by this point, and we can't tell what speed it was.
 939                  */
 940                 if (!list_empty(&dev->eps[i].bw_endpoint_list))
 941                         xhci_warn(xhci, "Slot %u endpoint %u "
 942                                         "not removed from BW list!\n",
 943                                         slot_id, i);
 944         }
 945         /* If this is a hub, free the TT(s) from the TT list */
 946         xhci_free_tt_info(xhci, dev, slot_id);
 947         /* If necessary, update the number of active TTs on this root port */
 948         xhci_update_tt_active_eps(xhci, dev, old_active_eps);
 949
 950         if (dev->ring_cache) {
 951                 for (i = 0; i < dev->num_rings_cached; i++)
 952                         xhci_ring_free(xhci, dev->ring_cache[i]);
 953                 kfree(dev->ring_cache);
 954         }
 955
 956         if (dev->in_ctx)
 957                 xhci_free_container_ctx(xhci, dev->in_ctx);
 958         if (dev->out_ctx)
 959                 xhci_free_container_ctx(xhci, dev->out_ctx);
 960
 961         kfree(xhci->devs[slot_id]);
 962         xhci->devs[slot_id] = NULL;
 963 }
 964
 965 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 966                 struct usb_device *udev, gfp_t flags)
 967 {
 968         struct xhci_virt_device *dev;
 969         int i;
 970
 971         /* Slot ID 0 is reserved */
 972         if (slot_id == 0 || xhci->devs[slot_id]) {
 973                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 974                 return 0;
 975         }
 976
 977         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 978         if (!xhci->devs[slot_id])
 979                 return 0;
 980         dev = xhci->devs[slot_id];
 981
 982         /* Allocate the (output) device context that will be used in the HC. */
 983         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 984         if (!dev->out_ctx)
 985                 goto fail;
 986
 987         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 988                         (unsigned long long)dev->out_ctx->dma);
 989
 990         /* Allocate the (input) device context for address device command */
 991         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 992         if (!dev->in_ctx)
 993                 goto fail;
 994
 995         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 996                         (unsigned long long)dev->in_ctx->dma);
 997
 998         /* Initialize the cancellation list and watchdog timers for each ep */
 999         for (i = 0; i < 31; i++) {
1000                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
1001                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
1002                 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
1003         }
1004
1005         /* Allocate endpoint 0 ring */
1006         dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags);
1007         if (!dev->eps[0].ring)
1008                 goto fail;
1009
1010         /* Allocate pointers to the ring cache */
1011         dev->ring_cache = kzalloc(
1012                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
1013                         flags);
1014         if (!dev->ring_cache)
1015                 goto fail;
1016         dev->num_rings_cached = 0;
1017
1018         init_completion(&dev->cmd_completion);
1019         dev->udev = udev;
1020
1021         /* Point to output device context in dcbaa. */
1022         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
1023         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
1024                  slot_id,
1025                  &xhci->dcbaa->dev_context_ptrs[slot_id],
1026                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
1027
1028         return 1;
1029 fail:
1030         xhci_free_virt_device(xhci, slot_id);
1031         return 0;
1032 }
1033
1034 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1035                 struct usb_device *udev)
1036 {
1037         struct xhci_virt_device *virt_dev;
1038         struct xhci_ep_ctx      *ep0_ctx;
1039         struct xhci_ring        *ep_ring;
1040
1041         virt_dev = xhci->devs[udev->slot_id];
1042         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1043         ep_ring = virt_dev->eps[0].ring;
1044         /*
1045          * FIXME we don't keep track of the dequeue pointer very well after a
1046          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1047          * host to our enqueue pointer.  This should only be called after a
1048          * configured device has reset, so all control transfers should have
1049          * been completed or cancelled before the reset.
1050          */
1051         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1052                                                         ep_ring->enqueue)
1053                                    | ep_ring->cycle_state);
1054 }
1055
1056 /*
1057  * The xHCI roothub may have ports of differing speeds in any order in the port
1058  * status registers.  xhci->port_array provides an array of the port speed for
1059  * each offset into the port status registers.
1060  *
1061  * The xHCI hardware wants to know the roothub port number that the USB device
1062  * is attached to (or the roothub port its ancestor hub is attached to).  All we
1063  * know is the index of that port under either the USB 2.0 or the USB 3.0
1064  * roothub, but that doesn't give us the real index into the HW port status
1065  * registers. Call xhci_find_raw_port_number() to get real index.
1066  */
1067 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1068                 struct usb_device *udev)
1069 {
1070         struct usb_device *top_dev;
1071         struct usb_hcd *hcd;
1072
1073         if (udev->speed >= USB_SPEED_SUPER)
1074                 hcd = xhci->shared_hcd;
1075         else
1076                 hcd = xhci->main_hcd;
1077
1078         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1079                         top_dev = top_dev->parent)
1080                 /* Found device below root hub */;
1081
1082         return  xhci_find_raw_port_number(hcd, top_dev->portnum);
1083 }
1084
1085 /* Setup an xHCI virtual device for a Set Address command */
1086 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1087 {
1088         struct xhci_virt_device *dev;
1089         struct xhci_ep_ctx      *ep0_ctx;
1090         struct xhci_slot_ctx    *slot_ctx;
1091         u32                     port_num;
1092         u32                     max_packets;
1093         struct usb_device *top_dev;
1094
1095         dev = xhci->devs[udev->slot_id];
1096         /* Slot ID 0 is reserved */
1097         if (udev->slot_id == 0 || !dev) {
1098                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1099                                 udev->slot_id);
1100                 return -EINVAL;
1101         }
1102         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1103         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1104
1105         /* 3) Only the control endpoint is valid - one endpoint context */
1106         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1107         switch (udev->speed) {
1108         case USB_SPEED_SUPER_PLUS:
1109                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP);
1110                 max_packets = MAX_PACKET(512);
1111                 break;
1112         case USB_SPEED_SUPER:
1113                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1114                 max_packets = MAX_PACKET(512);
1115                 break;
1116         case USB_SPEED_HIGH:
1117                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1118                 max_packets = MAX_PACKET(64);
1119                 break;
1120         /* USB core guesses at a 64-byte max packet first for FS devices */
1121         case USB_SPEED_FULL:
1122                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1123                 max_packets = MAX_PACKET(64);
1124                 break;
1125         case USB_SPEED_LOW:
1126                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1127                 max_packets = MAX_PACKET(8);
1128                 break;
1129         case USB_SPEED_WIRELESS:
1130                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1131                 return -EINVAL;
1132                 break;
1133         default:
1134                 /* Speed was set earlier, this shouldn't happen. */
1135                 return -EINVAL;
1136         }
1137         /* Find the root hub port this device is under */
1138         port_num = xhci_find_real_port_number(xhci, udev);
1139         if (!port_num)
1140                 return -EINVAL;
1141         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1142         /* Set the port number in the virtual_device to the faked port number */
1143         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1144                         top_dev = top_dev->parent)
1145                 /* Found device below root hub */;
1146         dev->fake_port = top_dev->portnum;
1147         dev->real_port = port_num;
1148         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1149         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1150
1151         /* Find the right bandwidth table that this device will be a part of.
1152          * If this is a full speed device attached directly to a root port (or a
1153          * decendent of one), it counts as a primary bandwidth domain, not a
1154          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1155          * will never be created for the HS root hub.
1156          */
1157         if (!udev->tt || !udev->tt->hub->parent) {
1158                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1159         } else {
1160                 struct xhci_root_port_bw_info *rh_bw;
1161                 struct xhci_tt_bw_info *tt_bw;
1162
1163                 rh_bw = &xhci->rh_bw[port_num - 1];
1164                 /* Find the right TT. */
1165                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1166                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1167                                 continue;
1168
1169                         if (!dev->udev->tt->multi ||
1170                                         (udev->tt->multi &&
1171                                          tt_bw->ttport == dev->udev->ttport)) {
1172                                 dev->bw_table = &tt_bw->bw_table;
1173                                 dev->tt_info = tt_bw;
1174                                 break;
1175                         }
1176                 }
1177                 if (!dev->tt_info)
1178                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1179         }
1180
1181         /* Is this a LS/FS device under an external HS hub? */
1182         if (udev->tt && udev->tt->hub->parent) {
1183                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1184                                                 (udev->ttport << 8));
1185                 if (udev->tt->multi)
1186                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1187         }
1188         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1189         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1190
1191         /* Step 4 - ring already allocated */
1192         /* Step 5 */
1193         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1194
1195         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1196         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1197                                          max_packets);
1198
1199         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1200                                    dev->eps[0].ring->cycle_state);
1201
1202         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1203
1204         return 0;
1205 }
1206
1207 /*
1208  * Convert interval expressed as 2^(bInterval - 1) == interval into
1209  * straight exponent value 2^n == interval.
1210  *
1211  */
1212 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1213                 struct usb_host_endpoint *ep)
1214 {
1215         unsigned int interval;
1216
1217         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1218         if (interval != ep->desc.bInterval - 1)
1219                 dev_warn(&udev->dev,
1220                          "ep %#x - rounding interval to %d %sframes\n",
1221                          ep->desc.bEndpointAddress,
1222                          1 << interval,
1223                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1224
1225         if (udev->speed == USB_SPEED_FULL) {
1226                 /*
1227                  * Full speed isoc endpoints specify interval in frames,
1228                  * not microframes. We are using microframes everywhere,
1229                  * so adjust accordingly.
1230                  */
1231                 interval += 3;  /* 1 frame = 2^3 uframes */
1232         }
1233
1234         return interval;
1235 }
1236
1237 /*
1238  * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1239  * microframes, rounded down to nearest power of 2.
1240  */
1241 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1242                 struct usb_host_endpoint *ep, unsigned int desc_interval,
1243                 unsigned int min_exponent, unsigned int max_exponent)
1244 {
1245         unsigned int interval;
1246
1247         interval = fls(desc_interval) - 1;
1248         interval = clamp_val(interval, min_exponent, max_exponent);
1249         if ((1 << interval) != desc_interval)
1250                 dev_dbg(&udev->dev,
1251                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1252                          ep->desc.bEndpointAddress,
1253                          1 << interval,
1254                          desc_interval);
1255
1256         return interval;
1257 }
1258
1259 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1260                 struct usb_host_endpoint *ep)
1261 {
1262         if (ep->desc.bInterval == 0)
1263                 return 0;
1264         return xhci_microframes_to_exponent(udev, ep,
1265                         ep->desc.bInterval, 0, 15);
1266 }
1267
1268
1269 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1270                 struct usb_host_endpoint *ep)
1271 {
1272         return xhci_microframes_to_exponent(udev, ep,
1273                         ep->desc.bInterval * 8, 3, 10);
1274 }
1275
1276 /* Return the polling or NAK interval.
1277  *
1278  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1279  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1280  *
1281  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1282  * is set to 0.
1283  */
1284 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1285                 struct usb_host_endpoint *ep)
1286 {
1287         unsigned int interval = 0;
1288
1289         switch (udev->speed) {
1290         case USB_SPEED_HIGH:
1291                 /* Max NAK rate */
1292                 if (usb_endpoint_xfer_control(&ep->desc) ||
1293                     usb_endpoint_xfer_bulk(&ep->desc)) {
1294                         interval = xhci_parse_microframe_interval(udev, ep);
1295                         break;
1296                 }
1297                 /* Fall through - SS and HS isoc/int have same decoding */
1298
1299         case USB_SPEED_SUPER_PLUS:
1300         case USB_SPEED_SUPER:
1301                 if (usb_endpoint_xfer_int(&ep->desc) ||
1302                     usb_endpoint_xfer_isoc(&ep->desc)) {
1303                         interval = xhci_parse_exponent_interval(udev, ep);
1304                 }
1305                 break;
1306
1307         case USB_SPEED_FULL:
1308                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1309                         interval = xhci_parse_exponent_interval(udev, ep);
1310                         break;
1311                 }
1312                 /*
1313                  * Fall through for interrupt endpoint interval decoding
1314                  * since it uses the same rules as low speed interrupt
1315                  * endpoints.
1316                  */
1317
1318         case USB_SPEED_LOW:
1319                 if (usb_endpoint_xfer_int(&ep->desc) ||
1320                     usb_endpoint_xfer_isoc(&ep->desc)) {
1321
1322                         interval = xhci_parse_frame_interval(udev, ep);
1323                 }
1324                 break;
1325
1326         default:
1327                 BUG();
1328         }
1329         return interval;
1330 }
1331
1332 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1333  * High speed endpoint descriptors can define "the number of additional
1334  * transaction opportunities per microframe", but that goes in the Max Burst
1335  * endpoint context field.
1336  */
1337 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1338                 struct usb_host_endpoint *ep)
1339 {
1340         if (udev->speed < USB_SPEED_SUPER ||
1341                         !usb_endpoint_xfer_isoc(&ep->desc))
1342                 return 0;
1343         return ep->ss_ep_comp.bmAttributes;
1344 }
1345
1346 static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
1347                                        struct usb_host_endpoint *ep)
1348 {
1349         /* Super speed and Plus have max burst in ep companion desc */
1350         if (udev->speed >= USB_SPEED_SUPER)
1351                 return ep->ss_ep_comp.bMaxBurst;
1352
1353         if (udev->speed == USB_SPEED_HIGH &&
1354             (usb_endpoint_xfer_isoc(&ep->desc) ||
1355              usb_endpoint_xfer_int(&ep->desc)))
1356                 return (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1357
1358         return 0;
1359 }
1360
1361 static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep)
1362 {
1363         int in;
1364
1365         in = usb_endpoint_dir_in(&ep->desc);
1366
1367         if (usb_endpoint_xfer_control(&ep->desc))
1368                 return CTRL_EP;
1369         if (usb_endpoint_xfer_bulk(&ep->desc))
1370                 return in ? BULK_IN_EP : BULK_OUT_EP;
1371         if (usb_endpoint_xfer_isoc(&ep->desc))
1372                 return in ? ISOC_IN_EP : ISOC_OUT_EP;
1373         if (usb_endpoint_xfer_int(&ep->desc))
1374                 return in ? INT_IN_EP : INT_OUT_EP;
1375         return 0;
1376 }
1377
1378 /* Return the maximum endpoint service interval time (ESIT) payload.
1379  * Basically, this is the maxpacket size, multiplied by the burst size
1380  * and mult size.
1381  */
1382 static u32 xhci_get_max_esit_payload(struct usb_device *udev,
1383                 struct usb_host_endpoint *ep)
1384 {
1385         int max_burst;
1386         int max_packet;
1387
1388         /* Only applies for interrupt or isochronous endpoints */
1389         if (usb_endpoint_xfer_control(&ep->desc) ||
1390                         usb_endpoint_xfer_bulk(&ep->desc))
1391                 return 0;
1392
1393         if (udev->speed >= USB_SPEED_SUPER)
1394                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1395
1396         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1397         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1398         /* A 0 in max burst means 1 transfer per ESIT */
1399         return max_packet * (max_burst + 1);
1400 }
1401
1402 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1403  * Drivers will have to call usb_alloc_streams() to do that.
1404  */
1405 int xhci_endpoint_init(struct xhci_hcd *xhci,
1406                 struct xhci_virt_device *virt_dev,
1407                 struct usb_device *udev,
1408                 struct usb_host_endpoint *ep,
1409                 gfp_t mem_flags)
1410 {
1411         unsigned int ep_index;
1412         struct xhci_ep_ctx *ep_ctx;
1413         struct xhci_ring *ep_ring;
1414         unsigned int max_packet;
1415         enum xhci_ring_type ring_type;
1416         u32 max_esit_payload;
1417         u32 endpoint_type;
1418         unsigned int max_burst;
1419         unsigned int interval;
1420         unsigned int mult;
1421         unsigned int avg_trb_len;
1422         unsigned int err_count = 0;
1423
1424         ep_index = xhci_get_endpoint_index(&ep->desc);
1425         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1426
1427         endpoint_type = xhci_get_endpoint_type(ep);
1428         if (!endpoint_type)
1429                 return -EINVAL;
1430
1431         ring_type = usb_endpoint_type(&ep->desc);
1432         /* Set up the endpoint ring */
1433         virt_dev->eps[ep_index].new_ring =
1434                 xhci_ring_alloc(xhci, 2, 1, ring_type, mem_flags);
1435         if (!virt_dev->eps[ep_index].new_ring) {
1436                 /* Attempt to use the ring cache */
1437                 if (virt_dev->num_rings_cached == 0)
1438                         return -ENOMEM;
1439                 virt_dev->num_rings_cached--;
1440                 virt_dev->eps[ep_index].new_ring =
1441                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1442                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1443                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1444                                         1, ring_type);
1445         }
1446         virt_dev->eps[ep_index].skip = false;
1447         ep_ring = virt_dev->eps[ep_index].new_ring;
1448
1449         /*
1450          * Get values to fill the endpoint context, mostly from ep descriptor.
1451          * The average TRB buffer lengt for bulk endpoints is unclear as we
1452          * have no clue on scatter gather list entry size. For Isoc and Int,
1453          * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
1454          */
1455         max_esit_payload = xhci_get_max_esit_payload(udev, ep);
1456         interval = xhci_get_endpoint_interval(udev, ep);
1457         mult = xhci_get_endpoint_mult(udev, ep);
1458         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1459         max_burst = xhci_get_endpoint_max_burst(udev, ep);
1460         avg_trb_len = max_esit_payload;
1461
1462         /* FIXME dig Mult and streams info out of ep companion desc */
1463
1464         /* Allow 3 retries for everything but isoc, set CErr = 3 */
1465         if (!usb_endpoint_xfer_isoc(&ep->desc))
1466                 err_count = 3;
1467         /* Some devices get this wrong */
1468         if (usb_endpoint_xfer_bulk(&ep->desc) && udev->speed == USB_SPEED_HIGH)
1469                 max_packet = 512;
1470         /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
1471         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100)
1472                 avg_trb_len = 8;
1473
1474         /* Fill the endpoint context */
1475         ep_ctx->ep_info = cpu_to_le32(EP_INTERVAL(interval) |
1476                                       EP_MULT(mult));
1477         ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) |
1478                                        MAX_PACKET(max_packet) |
1479                                        MAX_BURST(max_burst) |
1480                                        ERROR_COUNT(err_count));
1481         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma |
1482                                   ep_ring->cycle_state);
1483
1484         ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
1485                                       EP_AVG_TRB_LENGTH(avg_trb_len));
1486
1487         /* FIXME Debug endpoint context */
1488         return 0;
1489 }
1490
1491 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1492                 struct xhci_virt_device *virt_dev,
1493                 struct usb_host_endpoint *ep)
1494 {
1495         unsigned int ep_index;
1496         struct xhci_ep_ctx *ep_ctx;
1497
1498         ep_index = xhci_get_endpoint_index(&ep->desc);
1499         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1500
1501         ep_ctx->ep_info = 0;
1502         ep_ctx->ep_info2 = 0;
1503         ep_ctx->deq = 0;
1504         ep_ctx->tx_info = 0;
1505         /* Don't free the endpoint ring until the set interface or configuration
1506          * request succeeds.
1507          */
1508 }
1509
1510 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1511 {
1512         bw_info->ep_interval = 0;
1513         bw_info->mult = 0;
1514         bw_info->num_packets = 0;
1515         bw_info->max_packet_size = 0;
1516         bw_info->type = 0;
1517         bw_info->max_esit_payload = 0;
1518 }
1519
1520 void xhci_update_bw_info(struct xhci_hcd *xhci,
1521                 struct xhci_container_ctx *in_ctx,
1522                 struct xhci_input_control_ctx *ctrl_ctx,
1523                 struct xhci_virt_device *virt_dev)
1524 {
1525         struct xhci_bw_info *bw_info;
1526         struct xhci_ep_ctx *ep_ctx;
1527         unsigned int ep_type;
1528         int i;
1529
1530         for (i = 1; i < 31; ++i) {
1531                 bw_info = &virt_dev->eps[i].bw_info;
1532
1533                 /* We can't tell what endpoint type is being dropped, but
1534                  * unconditionally clearing the bandwidth info for non-periodic
1535                  * endpoints should be harmless because the info will never be
1536                  * set in the first place.
1537                  */
1538                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1539                         /* Dropped endpoint */
1540                         xhci_clear_endpoint_bw_info(bw_info);
1541                         continue;
1542                 }
1543
1544                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1545                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1546                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1547
1548                         /* Ignore non-periodic endpoints */
1549                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1550                                         ep_type != ISOC_IN_EP &&
1551                                         ep_type != INT_IN_EP)
1552                                 continue;
1553
1554                         /* Added or changed endpoint */
1555                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1556                                         le32_to_cpu(ep_ctx->ep_info));
1557                         /* Number of packets and mult are zero-based in the
1558                          * input context, but we want one-based for the
1559                          * interval table.
1560                          */
1561                         bw_info->mult = CTX_TO_EP_MULT(
1562                                         le32_to_cpu(ep_ctx->ep_info)) + 1;
1563                         bw_info->num_packets = CTX_TO_MAX_BURST(
1564                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1565                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1566                                         le32_to_cpu(ep_ctx->ep_info2));
1567                         bw_info->type = ep_type;
1568                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1569                                         le32_to_cpu(ep_ctx->tx_info));
1570                 }
1571         }
1572 }
1573
1574 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1575  * Useful when you want to change one particular aspect of the endpoint and then
1576  * issue a configure endpoint command.
1577  */
1578 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1579                 struct xhci_container_ctx *in_ctx,
1580                 struct xhci_container_ctx *out_ctx,
1581                 unsigned int ep_index)
1582 {
1583         struct xhci_ep_ctx *out_ep_ctx;
1584         struct xhci_ep_ctx *in_ep_ctx;
1585
1586         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1587         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1588
1589         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1590         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1591         in_ep_ctx->deq = out_ep_ctx->deq;
1592         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1593 }
1594
1595 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1596  * Useful when you want to change one particular aspect of the endpoint and then
1597  * issue a configure endpoint command.  Only the context entries field matters,
1598  * but we'll copy the whole thing anyway.
1599  */
1600 void xhci_slot_copy(struct xhci_hcd *xhci,
1601                 struct xhci_container_ctx *in_ctx,
1602                 struct xhci_container_ctx *out_ctx)
1603 {
1604         struct xhci_slot_ctx *in_slot_ctx;
1605         struct xhci_slot_ctx *out_slot_ctx;
1606
1607         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1608         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1609
1610         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1611         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1612         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1613         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1614 }
1615
1616 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1617 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1618 {
1619         int i;
1620         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1621         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1622
1623         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1624                         "Allocating %d scratchpad buffers", num_sp);
1625
1626         if (!num_sp)
1627                 return 0;
1628
1629         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1630         if (!xhci->scratchpad)
1631                 goto fail_sp;
1632
1633         xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1634                                      num_sp * sizeof(u64),
1635                                      &xhci->scratchpad->sp_dma, flags);
1636         if (!xhci->scratchpad->sp_array)
1637                 goto fail_sp2;
1638
1639         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1640         if (!xhci->scratchpad->sp_buffers)
1641                 goto fail_sp3;
1642
1643         xhci->scratchpad->sp_dma_buffers =
1644                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1645
1646         if (!xhci->scratchpad->sp_dma_buffers)
1647                 goto fail_sp4;
1648
1649         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1650         for (i = 0; i < num_sp; i++) {
1651                 dma_addr_t dma;
1652                 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1653                                 flags);
1654                 if (!buf)
1655                         goto fail_sp5;
1656
1657                 xhci->scratchpad->sp_array[i] = dma;
1658                 xhci->scratchpad->sp_buffers[i] = buf;
1659                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1660         }
1661
1662         return 0;
1663
1664  fail_sp5:
1665         for (i = i - 1; i >= 0; i--) {
1666                 dma_free_coherent(dev, xhci->page_size,
1667                                     xhci->scratchpad->sp_buffers[i],
1668                                     xhci->scratchpad->sp_dma_buffers[i]);
1669         }
1670         kfree(xhci->scratchpad->sp_dma_buffers);
1671
1672  fail_sp4:
1673         kfree(xhci->scratchpad->sp_buffers);
1674
1675  fail_sp3:
1676         dma_free_coherent(dev, num_sp * sizeof(u64),
1677                             xhci->scratchpad->sp_array,
1678                             xhci->scratchpad->sp_dma);
1679
1680  fail_sp2:
1681         kfree(xhci->scratchpad);
1682         xhci->scratchpad = NULL;
1683
1684  fail_sp:
1685         return -ENOMEM;
1686 }
1687
1688 static void scratchpad_free(struct xhci_hcd *xhci)
1689 {
1690         int num_sp;
1691         int i;
1692         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1693
1694         if (!xhci->scratchpad)
1695                 return;
1696
1697         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1698
1699         for (i = 0; i < num_sp; i++) {
1700                 dma_free_coherent(dev, xhci->page_size,
1701                                     xhci->scratchpad->sp_buffers[i],
1702                                     xhci->scratchpad->sp_dma_buffers[i]);
1703         }
1704         kfree(xhci->scratchpad->sp_dma_buffers);
1705         kfree(xhci->scratchpad->sp_buffers);
1706         dma_free_coherent(dev, num_sp * sizeof(u64),
1707                             xhci->scratchpad->sp_array,
1708                             xhci->scratchpad->sp_dma);
1709         kfree(xhci->scratchpad);
1710         xhci->scratchpad = NULL;
1711 }
1712
1713 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1714                 bool allocate_in_ctx, bool allocate_completion,
1715                 gfp_t mem_flags)
1716 {
1717         struct xhci_command *command;
1718
1719         command = kzalloc(sizeof(*command), mem_flags);
1720         if (!command)
1721                 return NULL;
1722
1723         if (allocate_in_ctx) {
1724                 command->in_ctx =
1725                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1726                                         mem_flags);
1727                 if (!command->in_ctx) {
1728                         kfree(command);
1729                         return NULL;
1730                 }
1731         }
1732
1733         if (allocate_completion) {
1734                 command->completion =
1735                         kzalloc(sizeof(struct completion), mem_flags);
1736                 if (!command->completion) {
1737                         xhci_free_container_ctx(xhci, command->in_ctx);
1738                         kfree(command);
1739                         return NULL;
1740                 }
1741                 init_completion(command->completion);
1742         }
1743
1744         command->status = 0;
1745         INIT_LIST_HEAD(&command->cmd_list);
1746         return command;
1747 }
1748
1749 void xhci_urb_free_priv(struct urb_priv *urb_priv)
1750 {
1751         if (urb_priv) {
1752                 kfree(urb_priv->td[0]);
1753                 kfree(urb_priv);
1754         }
1755 }
1756
1757 void xhci_free_command(struct xhci_hcd *xhci,
1758                 struct xhci_command *command)
1759 {
1760         xhci_free_container_ctx(xhci,
1761                         command->in_ctx);
1762         kfree(command->completion);
1763         kfree(command);
1764 }
1765
1766 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1767 {
1768         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
1769         int size;
1770         int i, j, num_ports;
1771
1772         del_timer_sync(&xhci->cmd_timer);
1773
1774         /* Free the Event Ring Segment Table and the actual Event Ring */
1775         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1776         if (xhci->erst.entries)
1777                 dma_free_coherent(dev, size,
1778                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1779         xhci->erst.entries = NULL;
1780         xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST");
1781         if (xhci->event_ring)
1782                 xhci_ring_free(xhci, xhci->event_ring);
1783         xhci->event_ring = NULL;
1784         xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring");
1785
1786         if (xhci->lpm_command)
1787                 xhci_free_command(xhci, xhci->lpm_command);
1788         xhci->lpm_command = NULL;
1789         if (xhci->cmd_ring)
1790                 xhci_ring_free(xhci, xhci->cmd_ring);
1791         xhci->cmd_ring = NULL;
1792         xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring");
1793         xhci_cleanup_command_queue(xhci);
1794
1795         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1796         for (i = 0; i < num_ports && xhci->rh_bw; i++) {
1797                 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1798                 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1799                         struct list_head *ep = &bwt->interval_bw[j].endpoints;
1800                         while (!list_empty(ep))
1801                                 list_del_init(ep->next);
1802                 }
1803         }
1804
1805         for (i = 1; i < MAX_HC_SLOTS; ++i)
1806                 xhci_free_virt_device(xhci, i);
1807
1808         dma_pool_destroy(xhci->segment_pool);
1809         xhci->segment_pool = NULL;
1810         xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool");
1811
1812         dma_pool_destroy(xhci->device_pool);
1813         xhci->device_pool = NULL;
1814         xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool");
1815
1816         dma_pool_destroy(xhci->small_streams_pool);
1817         xhci->small_streams_pool = NULL;
1818         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1819                         "Freed small stream array pool");
1820
1821         dma_pool_destroy(xhci->medium_streams_pool);
1822         xhci->medium_streams_pool = NULL;
1823         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1824                         "Freed medium stream array pool");
1825
1826         if (xhci->dcbaa)
1827                 dma_free_coherent(dev, sizeof(*xhci->dcbaa),
1828                                 xhci->dcbaa, xhci->dcbaa->dma);
1829         xhci->dcbaa = NULL;
1830
1831         scratchpad_free(xhci);
1832
1833         if (!xhci->rh_bw)
1834                 goto no_bw;
1835
1836         for (i = 0; i < num_ports; i++) {
1837                 struct xhci_tt_bw_info *tt, *n;
1838                 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1839                         list_del(&tt->tt_list);
1840                         kfree(tt);
1841                 }
1842         }
1843
1844 no_bw:
1845         xhci->cmd_ring_reserved_trbs = 0;
1846         xhci->num_usb2_ports = 0;
1847         xhci->num_usb3_ports = 0;
1848         xhci->num_active_eps = 0;
1849         kfree(xhci->usb2_ports);
1850         kfree(xhci->usb3_ports);
1851         kfree(xhci->port_array);
1852         kfree(xhci->rh_bw);
1853         kfree(xhci->ext_caps);
1854
1855         xhci->page_size = 0;
1856         xhci->page_shift = 0;
1857         xhci->bus_state[0].bus_suspended = 0;
1858         xhci->bus_state[1].bus_suspended = 0;
1859 }
1860
1861 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1862                 struct xhci_segment *input_seg,
1863                 union xhci_trb *start_trb,
1864                 union xhci_trb *end_trb,
1865                 dma_addr_t input_dma,
1866                 struct xhci_segment *result_seg,
1867                 char *test_name, int test_number)
1868 {
1869         unsigned long long start_dma;
1870         unsigned long long end_dma;
1871         struct xhci_segment *seg;
1872
1873         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1874         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1875
1876         seg = trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, false);
1877         if (seg != result_seg) {
1878                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1879                                 test_name, test_number);
1880                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1881                                 "input DMA 0x%llx\n",
1882                                 input_seg,
1883                                 (unsigned long long) input_dma);
1884                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1885                                 "ending TRB %p (0x%llx DMA)\n",
1886                                 start_trb, start_dma,
1887                                 end_trb, end_dma);
1888                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1889                                 result_seg, seg);
1890                 trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma,
1891                           true);
1892                 return -1;
1893         }
1894         return 0;
1895 }
1896
1897 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1898 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci)
1899 {
1900         struct {
1901                 dma_addr_t              input_dma;
1902                 struct xhci_segment     *result_seg;
1903         } simple_test_vector [] = {
1904                 /* A zeroed DMA field should fail */
1905                 { 0, NULL },
1906                 /* One TRB before the ring start should fail */
1907                 { xhci->event_ring->first_seg->dma - 16, NULL },
1908                 /* One byte before the ring start should fail */
1909                 { xhci->event_ring->first_seg->dma - 1, NULL },
1910                 /* Starting TRB should succeed */
1911                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1912                 /* Ending TRB should succeed */
1913                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1914                         xhci->event_ring->first_seg },
1915                 /* One byte after the ring end should fail */
1916                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1917                 /* One TRB after the ring end should fail */
1918                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1919                 /* An address of all ones should fail */
1920                 { (dma_addr_t) (~0), NULL },
1921         };
1922         struct {
1923                 struct xhci_segment     *input_seg;
1924                 union xhci_trb          *start_trb;
1925                 union xhci_trb          *end_trb;
1926                 dma_addr_t              input_dma;
1927                 struct xhci_segment     *result_seg;
1928         } complex_test_vector [] = {
1929                 /* Test feeding a valid DMA address from a different ring */
1930                 {       .input_seg = xhci->event_ring->first_seg,
1931                         .start_trb = xhci->event_ring->first_seg->trbs,
1932                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1933                         .input_dma = xhci->cmd_ring->first_seg->dma,
1934                         .result_seg = NULL,
1935                 },
1936                 /* Test feeding a valid end TRB from a different ring */
1937                 {       .input_seg = xhci->event_ring->first_seg,
1938                         .start_trb = xhci->event_ring->first_seg->trbs,
1939                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1940                         .input_dma = xhci->cmd_ring->first_seg->dma,
1941                         .result_seg = NULL,
1942                 },
1943                 /* Test feeding a valid start and end TRB from a different ring */
1944                 {       .input_seg = xhci->event_ring->first_seg,
1945                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1946                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1947                         .input_dma = xhci->cmd_ring->first_seg->dma,
1948                         .result_seg = NULL,
1949                 },
1950                 /* TRB in this ring, but after this TD */
1951                 {       .input_seg = xhci->event_ring->first_seg,
1952                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1953                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1954                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1955                         .result_seg = NULL,
1956                 },
1957                 /* TRB in this ring, but before this TD */
1958                 {       .input_seg = xhci->event_ring->first_seg,
1959                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1960                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1961                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1962                         .result_seg = NULL,
1963                 },
1964                 /* TRB in this ring, but after this wrapped TD */
1965                 {       .input_seg = xhci->event_ring->first_seg,
1966                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1967                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1968                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1969                         .result_seg = NULL,
1970                 },
1971                 /* TRB in this ring, but before this wrapped TD */
1972                 {       .input_seg = xhci->event_ring->first_seg,
1973                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1974                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1975                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1976                         .result_seg = NULL,
1977                 },
1978                 /* TRB not in this ring, and we have a wrapped TD */
1979                 {       .input_seg = xhci->event_ring->first_seg,
1980                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1981                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1982                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1983                         .result_seg = NULL,
1984                 },
1985         };
1986
1987         unsigned int num_tests;
1988         int i, ret;
1989
1990         num_tests = ARRAY_SIZE(simple_test_vector);
1991         for (i = 0; i < num_tests; i++) {
1992                 ret = xhci_test_trb_in_td(xhci,
1993                                 xhci->event_ring->first_seg,
1994                                 xhci->event_ring->first_seg->trbs,
1995                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1996                                 simple_test_vector[i].input_dma,
1997                                 simple_test_vector[i].result_seg,
1998                                 "Simple", i);
1999                 if (ret < 0)
2000                         return ret;
2001         }
2002
2003         num_tests = ARRAY_SIZE(complex_test_vector);
2004         for (i = 0; i < num_tests; i++) {
2005                 ret = xhci_test_trb_in_td(xhci,
2006                                 complex_test_vector[i].input_seg,
2007                                 complex_test_vector[i].start_trb,
2008                                 complex_test_vector[i].end_trb,
2009                                 complex_test_vector[i].input_dma,
2010                                 complex_test_vector[i].result_seg,
2011                                 "Complex", i);
2012                 if (ret < 0)
2013                         return ret;
2014         }
2015         xhci_dbg(xhci, "TRB math tests passed.\n");
2016         return 0;
2017 }
2018
2019 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2020 {
2021         u64 temp;
2022         dma_addr_t deq;
2023
2024         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2025                         xhci->event_ring->dequeue);
2026         if (deq == 0 && !in_interrupt())
2027                 xhci_warn(xhci, "WARN something wrong with SW event ring "
2028                                 "dequeue ptr.\n");
2029         /* Update HC event ring dequeue pointer */
2030         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2031         temp &= ERST_PTR_MASK;
2032         /* Don't clear the EHB bit (which is RW1C) because
2033          * there might be more events to service.
2034          */
2035         temp &= ~ERST_EHB;
2036         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2037                         "// Write event ring dequeue pointer, "
2038                         "preserving EHB bit");
2039         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2040                         &xhci->ir_set->erst_dequeue);
2041 }
2042
2043 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2044                 __le32 __iomem *addr, int max_caps)
2045 {
2046         u32 temp, port_offset, port_count;
2047         int i;
2048         u8 major_revision;
2049         struct xhci_hub *rhub;
2050
2051         temp = readl(addr);
2052         major_revision = XHCI_EXT_PORT_MAJOR(temp);
2053
2054         if (major_revision == 0x03) {
2055                 rhub = &xhci->usb3_rhub;
2056         } else if (major_revision <= 0x02) {
2057                 rhub = &xhci->usb2_rhub;
2058         } else {
2059                 xhci_warn(xhci, "Ignoring unknown port speed, "
2060                                 "Ext Cap %p, revision = 0x%x\n",
2061                                 addr, major_revision);
2062                 /* Ignoring port protocol we can't understand. FIXME */
2063                 return;
2064         }
2065         rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp);
2066         rhub->min_rev = XHCI_EXT_PORT_MINOR(temp);
2067
2068         /* Port offset and count in the third dword, see section 7.2 */
2069         temp = readl(addr + 2);
2070         port_offset = XHCI_EXT_PORT_OFF(temp);
2071         port_count = XHCI_EXT_PORT_COUNT(temp);
2072         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2073                         "Ext Cap %p, port offset = %u, "
2074                         "count = %u, revision = 0x%x",
2075                         addr, port_offset, port_count, major_revision);
2076         /* Port count includes the current port offset */
2077         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2078                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2079                 return;
2080
2081         rhub->psi_count = XHCI_EXT_PORT_PSIC(temp);
2082         if (rhub->psi_count) {
2083                 rhub->psi = kcalloc(rhub->psi_count, sizeof(*rhub->psi),
2084                                     GFP_KERNEL);
2085                 if (!rhub->psi)
2086                         rhub->psi_count = 0;
2087
2088                 rhub->psi_uid_count++;
2089                 for (i = 0; i < rhub->psi_count; i++) {
2090                         rhub->psi[i] = readl(addr + 4 + i);
2091
2092                         /* count unique ID values, two consecutive entries can
2093                          * have the same ID if link is assymetric
2094                          */
2095                         if (i && (XHCI_EXT_PORT_PSIV(rhub->psi[i]) !=
2096                                   XHCI_EXT_PORT_PSIV(rhub->psi[i - 1])))
2097                                 rhub->psi_uid_count++;
2098
2099                         xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
2100                                   XHCI_EXT_PORT_PSIV(rhub->psi[i]),
2101                                   XHCI_EXT_PORT_PSIE(rhub->psi[i]),
2102                                   XHCI_EXT_PORT_PLT(rhub->psi[i]),
2103                                   XHCI_EXT_PORT_PFD(rhub->psi[i]),
2104                                   XHCI_EXT_PORT_LP(rhub->psi[i]),
2105                                   XHCI_EXT_PORT_PSIM(rhub->psi[i]));
2106                 }
2107         }
2108         /* cache usb2 port capabilities */
2109         if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
2110                 xhci->ext_caps[xhci->num_ext_caps++] = temp;
2111
2112         /* Check the host's USB2 LPM capability */
2113         if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2114                         (temp & XHCI_L1C)) {
2115                 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2116                                 "xHCI 0.96: support USB2 software lpm");
2117                 xhci->sw_lpm_support = 1;
2118         }
2119
2120         if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2121                 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2122                                 "xHCI 1.0: support USB2 software lpm");
2123                 xhci->sw_lpm_support = 1;
2124                 if (temp & XHCI_HLC) {
2125                         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2126                                         "xHCI 1.0: support USB2 hardware lpm");
2127                         xhci->hw_lpm_support = 1;
2128                 }
2129         }
2130
2131         port_offset--;
2132         for (i = port_offset; i < (port_offset + port_count); i++) {
2133                 /* Duplicate entry.  Ignore the port if the revisions differ. */
2134                 if (xhci->port_array[i] != 0) {
2135                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2136                                         " port %u\n", addr, i);
2137                         xhci_warn(xhci, "Port was marked as USB %u, "
2138                                         "duplicated as USB %u\n",
2139                                         xhci->port_array[i], major_revision);
2140                         /* Only adjust the roothub port counts if we haven't
2141                          * found a similar duplicate.
2142                          */
2143                         if (xhci->port_array[i] != major_revision &&
2144                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
2145                                 if (xhci->port_array[i] == 0x03)
2146                                         xhci->num_usb3_ports--;
2147                                 else
2148                                         xhci->num_usb2_ports--;
2149                                 xhci->port_array[i] = DUPLICATE_ENTRY;
2150                         }
2151                         /* FIXME: Should we disable the port? */
2152                         continue;
2153                 }
2154                 xhci->port_array[i] = major_revision;
2155                 if (major_revision == 0x03)
2156                         xhci->num_usb3_ports++;
2157                 else
2158                         xhci->num_usb2_ports++;
2159         }
2160         /* FIXME: Should we disable ports not in the Extended Capabilities? */
2161 }
2162
2163 /*
2164  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2165  * specify what speeds each port is supposed to be.  We can't count on the port
2166  * speed bits in the PORTSC register being correct until a device is connected,
2167  * but we need to set up the two fake roothubs with the correct number of USB
2168  * 3.0 and USB 2.0 ports at host controller initialization time.
2169  */
2170 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2171 {
2172         void __iomem *base;
2173         u32 offset;
2174         unsigned int num_ports;
2175         int i, j, port_index;
2176         int cap_count = 0;
2177         u32 cap_start;
2178
2179         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2180         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2181         if (!xhci->port_array)
2182                 return -ENOMEM;
2183
2184         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2185         if (!xhci->rh_bw)
2186                 return -ENOMEM;
2187         for (i = 0; i < num_ports; i++) {
2188                 struct xhci_interval_bw_table *bw_table;
2189
2190                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2191                 bw_table = &xhci->rh_bw[i].bw_table;
2192                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2193                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2194         }
2195         base = &xhci->cap_regs->hc_capbase;
2196
2197         cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL);
2198         if (!cap_start) {
2199                 xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n");
2200                 return -ENODEV;
2201         }
2202
2203         offset = cap_start;
2204         /* count extended protocol capability entries for later caching */
2205         while (offset) {
2206                 cap_count++;
2207                 offset = xhci_find_next_ext_cap(base, offset,
2208                                                       XHCI_EXT_CAPS_PROTOCOL);
2209         }
2210
2211         xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags);
2212         if (!xhci->ext_caps)
2213                 return -ENOMEM;
2214
2215         offset = cap_start;
2216
2217         while (offset) {
2218                 xhci_add_in_port(xhci, num_ports, base + offset, cap_count);
2219                 if (xhci->num_usb2_ports + xhci->num_usb3_ports == num_ports)
2220                         break;
2221                 offset = xhci_find_next_ext_cap(base, offset,
2222                                                 XHCI_EXT_CAPS_PROTOCOL);
2223         }
2224
2225         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2226                 xhci_warn(xhci, "No ports on the roothubs?\n");
2227                 return -ENODEV;
2228         }
2229         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2230                         "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2231                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2232
2233         /* Place limits on the number of roothub ports so that the hub
2234          * descriptors aren't longer than the USB core will allocate.
2235          */
2236         if (xhci->num_usb3_ports > 15) {
2237                 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2238                                 "Limiting USB 3.0 roothub ports to 15.");
2239                 xhci->num_usb3_ports = 15;
2240         }
2241         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2242                 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2243                                 "Limiting USB 2.0 roothub ports to %u.",
2244                                 USB_MAXCHILDREN);
2245                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2246         }
2247
2248         /*
2249          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2250          * Not sure how the USB core will handle a hub with no ports...
2251          */
2252         if (xhci->num_usb2_ports) {
2253                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2254                                 xhci->num_usb2_ports, flags);
2255                 if (!xhci->usb2_ports)
2256                         return -ENOMEM;
2257
2258                 port_index = 0;
2259                 for (i = 0; i < num_ports; i++) {
2260                         if (xhci->port_array[i] == 0x03 ||
2261                                         xhci->port_array[i] == 0 ||
2262                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2263                                 continue;
2264
2265                         xhci->usb2_ports[port_index] =
2266                                 &xhci->op_regs->port_status_base +
2267                                 NUM_PORT_REGS*i;
2268                         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2269                                         "USB 2.0 port at index %u, "
2270                                         "addr = %p", i,
2271                                         xhci->usb2_ports[port_index]);
2272                         port_index++;
2273                         if (port_index == xhci->num_usb2_ports)
2274                                 break;
2275                 }
2276         }
2277         if (xhci->num_usb3_ports) {
2278                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2279                                 xhci->num_usb3_ports, flags);
2280                 if (!xhci->usb3_ports)
2281                         return -ENOMEM;
2282
2283                 port_index = 0;
2284                 for (i = 0; i < num_ports; i++)
2285                         if (xhci->port_array[i] == 0x03) {
2286                                 xhci->usb3_ports[port_index] =
2287                                         &xhci->op_regs->port_status_base +
2288                                         NUM_PORT_REGS*i;
2289                                 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2290                                                 "USB 3.0 port at index %u, "
2291                                                 "addr = %p", i,
2292                                                 xhci->usb3_ports[port_index]);
2293                                 port_index++;
2294                                 if (port_index == xhci->num_usb3_ports)
2295                                         break;
2296                         }
2297         }
2298         return 0;
2299 }
2300
2301 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2302 {
2303         dma_addr_t      dma;
2304         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2305         unsigned int    val, val2;
2306         u64             val_64;
2307         struct xhci_segment     *seg;
2308         u32 page_size, temp;
2309         int i;
2310
2311         INIT_LIST_HEAD(&xhci->cmd_list);
2312
2313         /* init command timeout timer */
2314         setup_timer(&xhci->cmd_timer, xhci_handle_command_timeout,
2315                     (unsigned long)xhci);
2316
2317         page_size = readl(&xhci->op_regs->page_size);
2318         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2319                         "Supported page size register = 0x%x", page_size);
2320         for (i = 0; i < 16; i++) {
2321                 if ((0x1 & page_size) != 0)
2322                         break;
2323                 page_size = page_size >> 1;
2324         }
2325         if (i < 16)
2326                 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2327                         "Supported page size of %iK", (1 << (i+12)) / 1024);
2328         else
2329                 xhci_warn(xhci, "WARN: no supported page size\n");
2330         /* Use 4K pages, since that's common and the minimum the HC supports */
2331         xhci->page_shift = 12;
2332         xhci->page_size = 1 << xhci->page_shift;
2333         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2334                         "HCD page size set to %iK", xhci->page_size / 1024);
2335
2336         /*
2337          * Program the Number of Device Slots Enabled field in the CONFIG
2338          * register with the max value of slots the HC can handle.
2339          */
2340         val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1));
2341         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2342                         "// xHC can handle at most %d device slots.", val);
2343         val2 = readl(&xhci->op_regs->config_reg);
2344         val |= (val2 & ~HCS_SLOTS_MASK);
2345         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2346                         "// Setting Max device slots reg = 0x%x.", val);
2347         writel(val, &xhci->op_regs->config_reg);
2348
2349         /*
2350          * Section 5.4.8 - doorbell array must be
2351          * "physically contiguous and 64-byte (cache line) aligned".
2352          */
2353         xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2354                         GFP_KERNEL);
2355         if (!xhci->dcbaa)
2356                 goto fail;
2357         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2358         xhci->dcbaa->dma = dma;
2359         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2360                         "// Device context base array address = 0x%llx (DMA), %p (virt)",
2361                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2362         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2363
2364         /*
2365          * Initialize the ring segment pool.  The ring must be a contiguous
2366          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2367          * however, the command ring segment needs 64-byte aligned segments
2368          * and our use of dma addresses in the trb_address_map radix tree needs
2369          * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2370          */
2371         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2372                         TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
2373
2374         /* See Table 46 and Note on Figure 55 */
2375         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2376                         2112, 64, xhci->page_size);
2377         if (!xhci->segment_pool || !xhci->device_pool)
2378                 goto fail;
2379
2380         /* Linear stream context arrays don't have any boundary restrictions,
2381          * and only need to be 16-byte aligned.
2382          */
2383         xhci->small_streams_pool =
2384                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2385                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2386         xhci->medium_streams_pool =
2387                 dma_pool_create("xHCI 1KB stream ctx arrays",
2388                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2389         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2390          * will be allocated with dma_alloc_coherent()
2391          */
2392
2393         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2394                 goto fail;
2395
2396         /* Set up the command ring to have one segments for now. */
2397         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2398         if (!xhci->cmd_ring)
2399                 goto fail;
2400         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2401                         "Allocated command ring at %p", xhci->cmd_ring);
2402         xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx",
2403                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2404
2405         /* Set the address in the Command Ring Control register */
2406         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2407         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2408                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2409                 xhci->cmd_ring->cycle_state;
2410         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2411                         "// Setting command ring address to 0x%x", val);
2412         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2413         xhci_dbg_cmd_ptrs(xhci);
2414
2415         xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
2416         if (!xhci->lpm_command)
2417                 goto fail;
2418
2419         /* Reserve one command ring TRB for disabling LPM.
2420          * Since the USB core grabs the shared usb_bus bandwidth mutex before
2421          * disabling LPM, we only need to reserve one TRB for all devices.
2422          */
2423         xhci->cmd_ring_reserved_trbs++;
2424
2425         val = readl(&xhci->cap_regs->db_off);
2426         val &= DBOFF_MASK;
2427         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2428                         "// Doorbell array is located at offset 0x%x"
2429                         " from cap regs base addr", val);
2430         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2431         xhci_dbg_regs(xhci);
2432         xhci_print_run_regs(xhci);
2433         /* Set ir_set to interrupt register set 0 */
2434         xhci->ir_set = &xhci->run_regs->ir_set[0];
2435
2436         /*
2437          * Event ring setup: Allocate a normal ring, but also setup
2438          * the event ring segment table (ERST).  Section 4.9.3.
2439          */
2440         xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring");
2441         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2442                                                 flags);
2443         if (!xhci->event_ring)
2444                 goto fail;
2445         if (xhci_check_trb_in_td_math(xhci) < 0)
2446                 goto fail;
2447
2448         xhci->erst.entries = dma_alloc_coherent(dev,
2449                         sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2450                         GFP_KERNEL);
2451         if (!xhci->erst.entries)
2452                 goto fail;
2453         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2454                         "// Allocated event ring segment table at 0x%llx",
2455                         (unsigned long long)dma);
2456
2457         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2458         xhci->erst.num_entries = ERST_NUM_SEGS;
2459         xhci->erst.erst_dma_addr = dma;
2460         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2461                         "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx",
2462                         xhci->erst.num_entries,
2463                         xhci->erst.entries,
2464                         (unsigned long long)xhci->erst.erst_dma_addr);
2465
2466         /* set ring base address and size for each segment table entry */
2467         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2468                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2469                 entry->seg_addr = cpu_to_le64(seg->dma);
2470                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2471                 entry->rsvd = 0;
2472                 seg = seg->next;
2473         }
2474
2475         /* set ERST count with the number of entries in the segment table */
2476         val = readl(&xhci->ir_set->erst_size);
2477         val &= ERST_SIZE_MASK;
2478         val |= ERST_NUM_SEGS;
2479         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2480                         "// Write ERST size = %i to ir_set 0 (some bits preserved)",
2481                         val);
2482         writel(val, &xhci->ir_set->erst_size);
2483
2484         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2485                         "// Set ERST entries to point to event ring.");
2486         /* set the segment table base address */
2487         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2488                         "// Set ERST base address for ir_set 0 = 0x%llx",
2489                         (unsigned long long)xhci->erst.erst_dma_addr);
2490         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2491         val_64 &= ERST_PTR_MASK;
2492         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2493         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2494
2495         /* Set the event ring dequeue address */
2496         xhci_set_hc_event_deq(xhci);
2497         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2498                         "Wrote ERST address to ir_set 0.");
2499         xhci_print_ir_set(xhci, 0);
2500
2501         /*
2502          * XXX: Might need to set the Interrupter Moderation Register to
2503          * something other than the default (~1ms minimum between interrupts).
2504          * See section 5.5.1.2.
2505          */
2506         init_completion(&xhci->addr_dev);
2507         for (i = 0; i < MAX_HC_SLOTS; ++i)
2508                 xhci->devs[i] = NULL;
2509         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2510                 xhci->bus_state[0].resume_done[i] = 0;
2511                 xhci->bus_state[1].resume_done[i] = 0;
2512                 /* Only the USB 2.0 completions will ever be used. */
2513                 init_completion(&xhci->bus_state[1].rexit_done[i]);
2514         }
2515
2516         if (scratchpad_alloc(xhci, flags))
2517                 goto fail;
2518         if (xhci_setup_port_arrays(xhci, flags))
2519                 goto fail;
2520
2521         /* Enable USB 3.0 device notifications for function remote wake, which
2522          * is necessary for allowing USB 3.0 devices to do remote wakeup from
2523          * U3 (device suspend).
2524          */
2525         temp = readl(&xhci->op_regs->dev_notification);
2526         temp &= ~DEV_NOTE_MASK;
2527         temp |= DEV_NOTE_FWAKE;
2528         writel(temp, &xhci->op_regs->dev_notification);
2529
2530         return 0;
2531
2532 fail:
2533         xhci_warn(xhci, "Couldn't initialize memory\n");
2534         xhci_halt(xhci);
2535         xhci_reset(xhci);
2536         xhci_mem_cleanup(xhci);
2537         return -ENOMEM;
2538 }