x86/platform/intel-mid: Keep SRAM powered on at boot

[cascardo/linux.git] / arch / x86 / platform / intel-mid / pwr.c

diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c
index 5bc90dd..5d3b45a 100644 (file)
--- a/arch/x86/platform/intel-mid/pwr.c
+++ b/arch/x86/platform/intel-mid/pwr.c
@@ -21,10 +21,9 @@
 
 #include <linux/delay.h>
 #include <linux/errno.h>
-#include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/export.h>
 #include <linux/mutex.h>
 #include <linux/pci.h>
 
@@ -45,7 +44,19 @@
 /* Bits in PM_CMD */
 #define PM_CMD_CMD(x)          ((x) << 0)
 #define PM_CMD_IOC             (1 << 8)
-#define PM_CMD_D3cold          (1 << 21)
+#define PM_CMD_CM_NOP          (0 << 9)
+#define PM_CMD_CM_IMMEDIATE    (1 << 9)
+#define PM_CMD_CM_DELAY                (2 << 9)
+#define PM_CMD_CM_TRIGGER      (3 << 9)
+
+/* System states */
+#define PM_CMD_SYS_STATE_S5    (5 << 16)
+
+/* Trigger variants */
+#define PM_CMD_CFG_TRIGGER_NC  (3 << 19)
+
+/* Message to wait for TRIGGER_NC case */
+#define TRIGGER_NC_MSG_2       (2 << 22)
 
 /* List of commands */
 #define CMD_SET_CFG            0x01
@@ -138,7 +149,7 @@ static int mid_pwr_wait(struct mid_pwr *pwr)
 
 static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd)
 {
-       writel(PM_CMD_CMD(cmd), pwr->regs + PM_CMD);
+       writel(PM_CMD_CMD(cmd) | PM_CMD_CM_IMMEDIATE, pwr->regs + PM_CMD);
        return mid_pwr_wait(pwr);
 }
 
@@ -261,6 +272,20 @@ int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
 }
 EXPORT_SYMBOL_GPL(intel_mid_pci_set_power_state);
 
+void intel_mid_pwr_power_off(void)
+{
+       struct mid_pwr *pwr = midpwr;
+       u32 cmd = PM_CMD_SYS_STATE_S5 |
+                 PM_CMD_CMD(CMD_SET_CFG) |
+                 PM_CMD_CM_TRIGGER |
+                 PM_CMD_CFG_TRIGGER_NC |
+                 TRIGGER_NC_MSG_2;
+
+       /* Send command to SCU */
+       writel(cmd, pwr->regs + PM_CMD);
+       mid_pwr_wait(pwr);
+}
+
 int intel_mid_pwr_get_lss_id(struct pci_dev *pdev)
 {
        int vndr;
@@ -355,7 +380,7 @@ static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
        return 0;
 }
 
-static int mid_set_initial_state(struct mid_pwr *pwr)
+static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states)
 {
        unsigned int i, j;
        int ret;
@@ -380,10 +405,10 @@ static int mid_set_initial_state(struct mid_pwr *pwr)
         * NOTE: The actual device mapping is provided by a platform at run
         * time using vendor capability of PCI configuration space.
         */
-       mid_pwr_set_state(pwr, 0, 0xffffffff);
-       mid_pwr_set_state(pwr, 1, 0xffffffff);
-       mid_pwr_set_state(pwr, 2, 0xffffffff);
-       mid_pwr_set_state(pwr, 3, 0xffffffff);
+       mid_pwr_set_state(pwr, 0, states[0]);
+       mid_pwr_set_state(pwr, 1, states[1]);
+       mid_pwr_set_state(pwr, 2, states[2]);
+       mid_pwr_set_state(pwr, 3, states[3]);
 
        /* Send command to SCU */
        ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
@@ -398,16 +423,43 @@ static int mid_set_initial_state(struct mid_pwr *pwr)
        return 0;
 }
 
-static const struct mid_pwr_device_info mid_info = {
-       .set_initial_state = mid_set_initial_state,
+static int pnw_set_initial_state(struct mid_pwr *pwr)
+{
+       /* On Penwell SRAM must stay powered on */
+       const u32 states[] = {
+               0xf00fffff,             /* PM_SSC(0) */
+               0xffffffff,             /* PM_SSC(1) */
+               0xffffffff,             /* PM_SSC(2) */
+               0xffffffff,             /* PM_SSC(3) */
+       };
+       return mid_set_initial_state(pwr, states);
+}
+
+static int tng_set_initial_state(struct mid_pwr *pwr)
+{
+       const u32 states[] = {
+               0xffffffff,             /* PM_SSC(0) */
+               0xffffffff,             /* PM_SSC(1) */
+               0xffffffff,             /* PM_SSC(2) */
+               0xffffffff,             /* PM_SSC(3) */
+       };
+       return mid_set_initial_state(pwr, states);
+}
+
+static const struct mid_pwr_device_info pnw_info = {
+       .set_initial_state = pnw_set_initial_state,
+};
+
+static const struct mid_pwr_device_info tng_info = {
+       .set_initial_state = tng_set_initial_state,
 };
 
+/* This table should be in sync with the one in drivers/pci/pci-mid.c */
 static const struct pci_device_id mid_pwr_pci_ids[] = {
-       { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
-       { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
+       { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&pnw_info },
+       { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info },
        {}
 };
-MODULE_DEVICE_TABLE(pci, mid_pwr_pci_ids);
 
 static struct pci_driver mid_pwr_pci_driver = {
        .name           = "intel_mid_pwr",