x86/platform/intel-mid: Keep SRAM powered on at boot

On Penwell SRAM has to be powered on, otherwise it prevents booting.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Fixes: ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")
Link: http://lkml.kernel.org/r/20160908103232.137587-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c
index 146ed54..5d3b45a 100644 (file)
--- a/arch/x86/platform/intel-mid/pwr.c
+++ b/arch/x86/platform/intel-mid/pwr.c
@@ -380,7 +380,7 @@ static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
        return 0;
 }
 
-static int mid_set_initial_state(struct mid_pwr *pwr)
+static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states)
 {
        unsigned int i, j;
        int ret;
@@ -405,10 +405,10 @@ static int mid_set_initial_state(struct mid_pwr *pwr)
         * NOTE: The actual device mapping is provided by a platform at run
         * time using vendor capability of PCI configuration space.
         */
-       mid_pwr_set_state(pwr, 0, 0xffffffff);
-       mid_pwr_set_state(pwr, 1, 0xffffffff);
-       mid_pwr_set_state(pwr, 2, 0xffffffff);
-       mid_pwr_set_state(pwr, 3, 0xffffffff);
+       mid_pwr_set_state(pwr, 0, states[0]);
+       mid_pwr_set_state(pwr, 1, states[1]);
+       mid_pwr_set_state(pwr, 2, states[2]);
+       mid_pwr_set_state(pwr, 3, states[3]);
 
        /* Send command to SCU */
        ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
@@ -423,14 +423,41 @@ static int mid_set_initial_state(struct mid_pwr *pwr)
        return 0;
 }
 
-static const struct mid_pwr_device_info mid_info = {
-       .set_initial_state = mid_set_initial_state,
+static int pnw_set_initial_state(struct mid_pwr *pwr)
+{
+       /* On Penwell SRAM must stay powered on */
+       const u32 states[] = {
+               0xf00fffff,             /* PM_SSC(0) */
+               0xffffffff,             /* PM_SSC(1) */
+               0xffffffff,             /* PM_SSC(2) */
+               0xffffffff,             /* PM_SSC(3) */
+       };
+       return mid_set_initial_state(pwr, states);
+}
+
+static int tng_set_initial_state(struct mid_pwr *pwr)
+{
+       const u32 states[] = {
+               0xffffffff,             /* PM_SSC(0) */
+               0xffffffff,             /* PM_SSC(1) */
+               0xffffffff,             /* PM_SSC(2) */
+               0xffffffff,             /* PM_SSC(3) */
+       };
+       return mid_set_initial_state(pwr, states);
+}
+
+static const struct mid_pwr_device_info pnw_info = {
+       .set_initial_state = pnw_set_initial_state,
+};
+
+static const struct mid_pwr_device_info tng_info = {
+       .set_initial_state = tng_set_initial_state,
 };
 
 /* This table should be in sync with the one in drivers/pci/pci-mid.c */
 static const struct pci_device_id mid_pwr_pci_ids[] = {
-       { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
-       { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
+       { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&pnw_info },
+       { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info },
        {}
 };