1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
4 double bit errors which are uncorrectable.
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
20 interrupt. Note the rising edge type.
24 - compatible : Should be "altr,socfpga-ocram-ecc"
25 - reg : Address and size for ECC error interrupt clear registers.
26 - iram : phandle to On-Chip RAM definition.
27 - interrupts : Should be single bit error interrupt, then double bit error
28 interrupt. Note the rising edge type.
32 eccmgr: eccmgr@ffd08140 {
33 compatible = "altr,socfpga-ecc-manager";
39 compatible = "altr,socfpga-l2-ecc";
40 reg = <0xffd08140 0x4>;
41 interrupts = <0 36 1>, <0 37 1>;
45 compatible = "altr,socfpga-ocram-ecc";
46 reg = <0xffd08144 0x4>;
48 interrupts = <0 178 1>, <0 179 1>;
52 Arria10 SoCFPGA ECC Manager
53 The Arria10 SoC ECC Manager handles the IRQs for each peripheral
54 in a shared register instead of individual IRQs like the Cyclone5
55 and Arria5. Therefore the device tree is different as well.
58 - compatible : Should be "altr,socfpga-a10-ecc-manager"
59 - altr,sysgr-syscon : phandle to Arria10 System Manager Block
60 containing the ECC manager registers.
61 - #address-cells: must be 1
62 - #size-cells: must be 1
63 - interrupts : Should be single bit error interrupt, then double bit error
65 - interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
66 - #interrupt-cells : must be set to 2.
67 - ranges : standard definition, should translate from local addresses
73 - compatible : Should be "altr,socfpga-a10-l2-ecc"
74 - reg : Address and size for ECC error interrupt clear registers.
75 - interrupts : Should be single bit error interrupt, then double bit error
76 interrupt, in this order.
80 - compatible : Should be "altr,socfpga-a10-ocram-ecc"
81 - reg : Address and size for ECC block registers.
82 - interrupts : Should be single bit error interrupt, then double bit error
83 interrupt, in this order.
87 - compatible : Should be "altr,socfpga-eth-mac-ecc"
88 - reg : Address and size for ECC block registers.
89 - altr,ecc-parent : phandle to parent Ethernet node.
90 - interrupts : Should be single bit error interrupt, then double bit error
91 interrupt, in this order.
95 eccmgr: eccmgr@ffd06000 {
96 compatible = "altr,socfpga-a10-ecc-manager";
97 altr,sysmgr-syscon = <&sysmgr>;
100 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
101 <0 0 IRQ_TYPE_LEVEL_HIGH>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
107 compatible = "altr,socfpga-a10-l2-ecc";
108 reg = <0xffd06010 0x4>;
109 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
110 <32 IRQ_TYPE_LEVEL_HIGH>;
114 compatible = "altr,socfpga-a10-ocram-ecc";
115 reg = <0xff8c3000 0x90>;
116 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
117 <33 IRQ_TYPE_LEVEL_HIGH> ;
120 emac0-rx-ecc@ff8c0800 {
121 compatible = "altr,socfpga-eth-mac-ecc";
122 reg = <0xff8c0800 0x400>;
123 altr,ecc-parent = <&gmac0>;
124 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
125 <36 IRQ_TYPE_LEVEL_HIGH>;
128 emac0-tx-ecc@ff8c0c00 {
129 compatible = "altr,socfpga-eth-mac-ecc";
130 reg = <0xff8c0c00 0x400>;
131 altr,ecc-parent = <&gmac0>;
132 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
133 <37 IRQ_TYPE_LEVEL_HIGH>;