1 Hisilicon Platforms Device Tree Bindings
2 ----------------------------------------------------
4 Required root node properties:
5 - compatible = "hisilicon,hi3620-hi4511";
8 Required root node properties:
9 - compatible = "hisilicon,hi6220";
12 Required root node properties:
13 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
16 Required root node properties:
17 - compatible = "hisilicon,hip01-ca9x2";
20 Required root node properties:
21 - compatible = "hisilicon,hip04-d01";
24 Required root node properties:
25 - compatible = "hisilicon,hip05-d02";
28 Required root node properties:
29 - compatible = "hisilicon,hip06-d03";
31 Hisilicon system controller
34 - compatible : "hisilicon,sysctrl"
35 - reg : Register address and size
38 - smp-offset : offset in sysctrl for notifying slave cpu booting
42 If reg value is not zero, cpun exit wfi and go
43 - resume-offset : offset in sysctrl for notifying cpu0 when resume
44 - reboot-offset : offset in sysctrl for system reboot
49 sysctrl: system-controller@fc802000 {
50 compatible = "hisilicon,sysctrl";
51 reg = <0xfc802000 0x1000>;
53 resume-offset = <0x308>;
54 reboot-offset = <0x4>;
57 -----------------------------------------------------------------------
58 Hisilicon Hi6220 system controller
61 - compatible : "hisilicon,hi6220-sysctrl"
62 - reg : Register address and size
63 - #clock-cells: should be set to 1, many clock registers are defined
64 under this controller and this property must be present.
66 Hisilicon designs this controller as one of the system controllers,
67 its main functions are the same as Hisilicon system controller, but
68 the register offset of some core modules are different.
72 sys_ctrl: sys_ctrl@f7030000 {
73 compatible = "hisilicon,hi6220-sysctrl", "syscon";
74 reg = <0x0 0xf7030000 0x0 0x2000>;
79 Hisilicon Hi6220 Power Always ON domain controller
82 - compatible : "hisilicon,hi6220-aoctrl"
83 - reg : Register address and size
84 - #clock-cells: should be set to 1, many clock registers are defined
85 under this controller and this property must be present.
87 Hisilicon designs this system controller to control the power always
88 on domain for mobile platform.
92 ao_ctrl: ao_ctrl@f7800000 {
93 compatible = "hisilicon,hi6220-aoctrl", "syscon";
94 reg = <0x0 0xf7800000 0x0 0x2000>;
99 Hisilicon Hi6220 Media domain controller
102 - compatible : "hisilicon,hi6220-mediactrl"
103 - reg : Register address and size
104 - #clock-cells: should be set to 1, many clock registers are defined
105 under this controller and this property must be present.
107 Hisilicon designs this system controller to control the multimedia
108 domain(e.g. codec, G3D ...) for mobile platform.
112 media_ctrl: media_ctrl@f4410000 {
113 compatible = "hisilicon,hi6220-mediactrl", "syscon";
114 reg = <0x0 0xf4410000 0x0 0x1000>;
119 Hisilicon Hi6220 Power Management domain controller
122 - compatible : "hisilicon,hi6220-pmctrl"
123 - reg : Register address and size
124 - #clock-cells: should be set to 1, some clock registers are define
125 under this controller and this property must be present.
127 Hisilicon designs this system controller to control the power management
128 domain for mobile platform.
132 pm_ctrl: pm_ctrl@f7032000 {
133 compatible = "hisilicon,hi6220-pmctrl", "syscon";
134 reg = <0x0 0xf7032000 0x0 0x1000>;
139 Hisilicon Hi6220 SRAM controller
142 - compatible : "hisilicon,hi6220-sramctrl", "syscon"
143 - reg : Register address and size
145 Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
146 SRAM banks for power management, modem, security, etc. Further, use "syscon"
147 managing the common sram which can be shared by multiple modules.
151 sram: sram@fff80000 {
152 compatible = "hisilicon,hi6220-sramctrl", "syscon";
153 reg = <0x0 0xfff80000 0x0 0x12000>;
156 -----------------------------------------------------------------------
157 Hisilicon HiP01 system controller
160 - compatible : "hisilicon,hip01-sysctrl"
161 - reg : Register address and size
163 The HiP01 system controller is mostly compatible with hisilicon
164 system controller,but it has some specific control registers for
165 HIP01 SoC family, such as slave core boot, and also some same
166 registers located at different offset.
170 /* for hip01-ca9x2 */
171 sysctrl: system-controller@10000000 {
172 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
173 reg = <0x10000000 0x1000>;
174 reboot-offset = <0x4>;
177 -----------------------------------------------------------------------
178 Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
181 - compatible : "hisilicon,pcie-sas-subctrl", "syscon";
182 - reg : Register address and size
184 The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
185 HiP05 or HiP06 Soc to implement some basic configurations.
188 /* for HiP05 PCIe-SAS sub system */
189 pcie_sas: system_controller@b0000000 {
190 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
191 reg = <0xb0000000 0x10000>;
194 Hisilicon HiP05/HiP06 PERI sub system controller
197 - compatible : "hisilicon,peri-subctrl", "syscon";
198 - reg : Register address and size
200 The PERI sub system controller is shared by peripheral controllers in
201 HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
202 controllers include mdio, ddr, iic, uart, timer and so on.
205 /* for HiP05 sub peri system */
206 peri_c_subctrl: syscon@80000000 {
207 compatible = "hisilicon,peri-subctrl", "syscon";
208 reg = <0x0 0x80000000 0x0 0x10000>;
211 Hisilicon HiP05/HiP06 DSA sub system controller
214 - compatible : "hisilicon,dsa-subctrl", "syscon";
215 - reg : Register address and size
217 The DSA sub system controller is shared by peripheral controllers in
218 HiP05 or HiP06 Soc to implement some basic configurations.
221 /* for HiP05 dsa sub system */
222 pcie_sas: system_controller@a0000000 {
223 compatible = "hisilicon,dsa-subctrl", "syscon";
224 reg = <0xa0000000 0x10000>;
227 -----------------------------------------------------------------------
228 Hisilicon CPU controller
231 - compatible : "hisilicon,cpuctrl"
232 - reg : Register address and size
234 The clock registers and power registers of secondary cores are defined
235 in CPU controller, especially in HIX5HD2 SoC.
237 -----------------------------------------------------------------------
238 PCTRL: Peripheral misc control register
241 - compatible: "hisilicon,pctrl"
242 - reg: Address and size of pctrl.
247 pctrl: pctrl@fca09000 {
248 compatible = "hisilicon,pctrl";
249 reg = <0xfca09000 0x1000>;
252 -----------------------------------------------------------------------
256 - compatible: "hisilicon,hip04-fabric";
257 - reg: Address and size of Fabric
259 -----------------------------------------------------------------------
260 Bootwrapper boot method (software protocol on SMP):
263 - compatible: "hisilicon,hip04-bootwrapper";
264 - boot-method: Address and size of boot method.
265 [0]: bootwrapper physical address
266 [1]: bootwrapper size
267 [2]: relocation physical address