3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
6 It is possible, but not required, to represent each port as a sub-node.
7 It allows to enable each port independently when dealing with multiple
11 - compatible : compatible string, one of:
12 - "allwinner,sun4i-a10-ahci"
13 - "hisilicon,hisi-ahci"
15 - "marvell,armada-380-ahci"
16 - "marvell,armada-3700-ahci"
18 - "snps,exynos5440-ahci"
21 - interrupts : <interrupt mapping for SATA IRQ>
22 - reg : <registers mapping>
24 Please note that when using "generic-ahci" you must also specify a SoC specific
26 compatible = "manufacturer,soc-model-ahci", "generic-ahci";
29 - dma-coherent : Present if dma operations are coherent
30 - clocks : a list of phandle + clock specifier pairs
31 - target-supply : regulator for SATA target power
32 - phys : reference to the SATA PHY node
33 - phy-names : must be "sata-phy"
35 Required properties when using sub-nodes:
36 - #address-cells : number of cells to encode an address
37 - #size-cells : number of cells representing the size of an address
40 Sub-nodes required properties:
41 - reg : the port number
42 And at least one of the following properties:
43 - phys : reference to the SATA PHY node
44 - target-supply : regulator for SATA target power
48 compatible = "snps,spear-ahci";
49 reg = <0xffe08000 0x1000>;
54 compatible = "allwinner,sun4i-a10-ahci";
55 reg = <0x01c18000 0x1000>;
57 clocks = <&pll6 0>, <&ahb_gates 25>;
58 target-supply = <®_ahci_5v>;
63 compatible = "marvell,berlin2q-achi", "generic-ahci";
64 reg = <0xe90000 0x1000>;
65 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
66 clocks = <&chip CLKID_SATA>;
73 target-supply = <®_sata0>;
79 target-supply = <®_sata1>;;