Documentation/devicetree/bindings/clock/sunxi.txt

   1 Device Tree Clock bindings for arch-sunxi
   2
   3 This binding uses the common clock binding[1].
   4
   5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
   6
   7 Required properties:
   8 - compatible : shall be one of the following:
   9         "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
  10         "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
  11         "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
  12         "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
  13         "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
  14         "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
  15         "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
  16         "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
  17         "allwinner,sun4i-a10-axi-clk" - for the AXI clock
  18         "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
  19         "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
  20         "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
  21         "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
  22         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
  23         "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
  24         "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
  25         "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
  26         "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
  27         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
  28         "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
  29         "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
  30         "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
  31         "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
  32         "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
  33         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
  34         "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
  35         "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
  36         "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
  37         "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
  38         "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
  39         "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
  40         "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
  41         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
  42         "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
  43         "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
  44         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
  45         "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
  46         "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
  47         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
  48         "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
  49         "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
  50         "allwinner,sun7i-a20-out-clk" - for the external output clocks
  51         "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
  52         "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
  53         "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
  54         "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
  55
  56 Required properties for all clocks:
  57 - reg : shall be the control register address for the clock.
  58 - clocks : shall be the input parent clock(s) phandle for the clock. For
  59         multiplexed clocks, the list order must match the hardware
  60         programming order.
  61 - #clock-cells : from common clock binding; shall be set to 0 except for
  62         "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
  63         "allwinner,sun4i-pll6-clk" where it shall be set to 1
  64 - clock-output-names : shall be the corresponding names of the outputs.
  65         If the clock module only has one output, the name shall be the
  66         module name.
  67
  68 And "allwinner,*-usb-clk" clocks also require:
  69 - reset-cells : shall be set to 1
  70
  71 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
  72 dummy clocks at 25 MHz and 125 MHz, respectively. See example.
  73
  74 Clock consumers should specify the desired clocks they use with a
  75 "clocks" phandle cell. Consumers that are using a gated clock should
  76 provide an additional ID in their clock property. This ID is the
  77 offset of the bit controlling this particular gate in the register.
  78
  79 For example:
  80
  81 osc24M: clk@01c20050 {
  82         #clock-cells = <0>;
  83         compatible = "allwinner,sun4i-a10-osc-clk";
  84         reg = <0x01c20050 0x4>;
  85         clocks = <&osc24M_fixed>;
  86         clock-output-names = "osc24M";
  87 };
  88
  89 pll1: clk@01c20000 {
  90         #clock-cells = <0>;
  91         compatible = "allwinner,sun4i-a10-pll1-clk";
  92         reg = <0x01c20000 0x4>;
  93         clocks = <&osc24M>;
  94         clock-output-names = "pll1";
  95 };
  96
  97 pll5: clk@01c20020 {
  98         #clock-cells = <1>;
  99         compatible = "allwinner,sun4i-pll5-clk";
 100         reg = <0x01c20020 0x4>;
 101         clocks = <&osc24M>;
 102         clock-output-names = "pll5_ddr", "pll5_other";
 103 };
 104
 105 cpu: cpu@01c20054 {
 106         #clock-cells = <0>;
 107         compatible = "allwinner,sun4i-a10-cpu-clk";
 108         reg = <0x01c20054 0x4>;
 109         clocks = <&osc32k>, <&osc24M>, <&pll1>;
 110         clock-output-names = "cpu";
 111 };
 112
 113 mmc0_clk: clk@01c20088 {
 114         #clock-cells = <0>;
 115         compatible = "allwinner,sun4i-mod0-clk";
 116         reg = <0x01c20088 0x4>;
 117         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 118         clock-output-names = "mmc0";
 119 };
 120
 121 mii_phy_tx_clk: clk@2 {
 122         #clock-cells = <0>;
 123         compatible = "fixed-clock";
 124         clock-frequency = <25000000>;
 125         clock-output-names = "mii_phy_tx";
 126 };
 127
 128 gmac_int_tx_clk: clk@3 {
 129         #clock-cells = <0>;
 130         compatible = "fixed-clock";
 131         clock-frequency = <125000000>;
 132         clock-output-names = "gmac_int_tx";
 133 };
 134
 135 gmac_clk: clk@01c20164 {
 136         #clock-cells = <0>;
 137         compatible = "allwinner,sun7i-a20-gmac-clk";
 138         reg = <0x01c20164 0x4>;
 139         /*
 140          * The first clock must be fixed at 25MHz;
 141          * the second clock must be fixed at 125MHz
 142          */
 143         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 144         clock-output-names = "gmac";
 145 };