1 Device Tree Clock bindings for arch-sunxi
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
14 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
15 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
16 "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
17 "allwinner,sun4i-a10-axi-clk" - for the AXI clock
18 "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
19 "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
20 "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
21 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
22 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
23 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
24 "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
25 "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
26 "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
27 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
28 "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
29 "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
30 "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
31 "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
32 "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
33 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
34 "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
35 "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
36 "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
37 "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
38 "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
39 "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
40 "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
41 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
42 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
43 "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
44 "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
45 "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
46 "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
47 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
48 "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
49 "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
50 "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
51 "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
52 "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
53 "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
54 "allwinner,sun7i-a20-out-clk" - for the external output clocks
55 "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
56 "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
57 "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
58 "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
60 Required properties for all clocks:
61 - reg : shall be the control register address for the clock.
62 - clocks : shall be the input parent clock(s) phandle for the clock. For
63 multiplexed clocks, the list order must match the hardware
65 - #clock-cells : from common clock binding; shall be set to 0 except for
66 "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
67 "allwinner,sun4i-pll6-clk" where it shall be set to 1
68 - clock-output-names : shall be the corresponding names of the outputs.
69 If the clock module only has one output, the name shall be the
72 And "allwinner,*-usb-clk" clocks also require:
73 - reset-cells : shall be set to 1
75 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
76 dummy clocks at 25 MHz and 125 MHz, respectively. See example.
78 Clock consumers should specify the desired clocks they use with a
79 "clocks" phandle cell. Consumers that are using a gated clock should
80 provide an additional ID in their clock property. This ID is the
81 offset of the bit controlling this particular gate in the register.
85 osc24M: clk@01c20050 {
87 compatible = "allwinner,sun4i-a10-osc-clk";
88 reg = <0x01c20050 0x4>;
89 clocks = <&osc24M_fixed>;
90 clock-output-names = "osc24M";
95 compatible = "allwinner,sun4i-a10-pll1-clk";
96 reg = <0x01c20000 0x4>;
98 clock-output-names = "pll1";
103 compatible = "allwinner,sun4i-pll5-clk";
104 reg = <0x01c20020 0x4>;
106 clock-output-names = "pll5_ddr", "pll5_other";
111 compatible = "allwinner,sun4i-a10-cpu-clk";
112 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&pll1>;
114 clock-output-names = "cpu";
117 mmc0_clk: clk@01c20088 {
119 compatible = "allwinner,sun4i-mod0-clk";
120 reg = <0x01c20088 0x4>;
121 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
122 clock-output-names = "mmc0";
125 mii_phy_tx_clk: clk@2 {
127 compatible = "fixed-clock";
128 clock-frequency = <25000000>;
129 clock-output-names = "mii_phy_tx";
132 gmac_int_tx_clk: clk@3 {
134 compatible = "fixed-clock";
135 clock-frequency = <125000000>;
136 clock-output-names = "gmac_int_tx";
139 gmac_clk: clk@01c20164 {
141 compatible = "allwinner,sun7i-a20-gmac-clk";
142 reg = <0x01c20164 0x4>;
144 * The first clock must be fixed at 25MHz;
145 * the second clock must be fixed at 125MHz
147 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
148 clock-output-names = "gmac";