Documentation/devicetree/bindings/display/renesas,du.txt

   1 * Renesas R-Car Display Unit (DU)
   2
   3 Required Properties:
   4
   5   - compatible: must be one of the following.
   6     - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
   7     - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
   8     - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
   9     - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
  10     - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
  11     - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
  12
  13   - reg: A list of base address and length of each memory resource, one for
  14     each entry in the reg-names property.
  15   - reg-names: Name of the memory resources. The DU requires one memory
  16     resource for the DU core (named "du") and one memory resource for each
  17     LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
  18     index).
  19
  20   - interrupt-parent: phandle of the parent interrupt controller.
  21   - interrupts: Interrupt specifiers for the DU interrupts.
  22
  23   - clocks: A list of phandles + clock-specifier pairs, one for each entry in
  24     the clock-names property.
  25   - clock-names: Name of the clocks. This property is model-dependent.
  26     - R8A7779 uses a single functional clock. The clock doesn't need to be
  27       named.
  28     - R8A779[01345] use one functional clock per channel and one clock per LVDS
  29       encoder (if available). The functional clocks must be named "du.x" with
  30       "x" being the channel numerical index. The LVDS clocks must be named
  31       "lvds.x" with "x" being the LVDS encoder numerical index.
  32     - In addition to the functional and encoder clocks, all DU versions also
  33       support externally supplied pixel clocks. Those clocks are optional.
  34       When supplied they must be named "dclkin.x" with "x" being the input
  35       clock numerical index.
  36
  37 Required nodes:
  38
  39 The connections to the DU output video ports are modeled using the OF graph
  40 bindings specified in Documentation/devicetree/bindings/graph.txt.
  41
  42 The following table lists for each supported model the port number
  43 corresponding to each DU output.
  44
  45                 Port 0          Port1           Port2           Port3
  46 -----------------------------------------------------------------------------
  47  R8A7779 (H1)   DPAD 0          DPAD 1          -               -
  48  R8A7790 (H2)   DPAD            LVDS 0          LVDS 1          -
  49  R8A7791 (M2-W) DPAD            LVDS 0          -               -
  50  R8A7793 (M2-N) DPAD            LVDS 0          -               -
  51  R8A7794 (E2)   DPAD 0          DPAD 1          -               -
  52  R8A7795 (H3)   DPAD            HDMI 0          HDMI 1          LVDS
  53
  54
  55 Example: R8A7790 (R-Car H2) DU
  56
  57         du: du@feb00000 {
  58                 compatible = "renesas,du-r8a7790";
  59                 reg = <0 0xfeb00000 0 0x70000>,
  60                       <0 0xfeb90000 0 0x1c>,
  61                       <0 0xfeb94000 0 0x1c>;
  62                 reg-names = "du", "lvds.0", "lvds.1";
  63                 interrupt-parent = <&gic>;
  64                 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
  65                              <0 268 IRQ_TYPE_LEVEL_HIGH>,
  66                              <0 269 IRQ_TYPE_LEVEL_HIGH>;
  67                 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
  68                          <&mstp7_clks R8A7790_CLK_DU1>,
  69                          <&mstp7_clks R8A7790_CLK_DU2>,
  70                          <&mstp7_clks R8A7790_CLK_LVDS0>,
  71                          <&mstp7_clks R8A7790_CLK_LVDS1>;
  72                 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
  73
  74                 ports {
  75                         #address-cells = <1>;
  76                         #size-cells = <0>;
  77
  78                         port@0 {
  79                                 reg = <0>;
  80                                 du_out_rgb: endpoint {
  81                                 };
  82                         };
  83                         port@1 {
  84                                 reg = <1>;
  85                                 du_out_lvds0: endpoint {
  86                                 };
  87                         };
  88                         port@2 {
  89                                 reg = <2>;
  90                                 du_out_lvds1: endpoint {
  91                                 };
  92                         };
  93                 };
  94         };