4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
8 in the host1x address space. Should be 1.
9 - #size-cells: The number of cells used to represent the size of an address
10 range in the host1x address space. Should be 1.
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
15 See ../reset/reset.txt for details.
16 - reset-names: Must include the following entries:
19 The host1x top-level node defines a number of children, each representing one
20 of the following host1x client modules:
25 - compatible: "nvidia,tegra<chip>-mpe"
26 - reg: Physical base address and length of the controller's registers.
27 - interrupts: The interrupt outputs from the controller.
28 - clocks: Must contain one entry, for the module clock.
29 See ../clocks/clock-bindings.txt for details.
30 - resets: Must contain an entry for each entry in reset-names.
31 See ../reset/reset.txt for details.
32 - reset-names: Must include the following entries:
38 - compatible: "nvidia,tegra<chip>-vi"
39 - reg: Physical base address and length of the controller's registers.
40 - interrupts: The interrupt outputs from the controller.
41 - clocks: Must contain one entry, for the module clock.
42 See ../clocks/clock-bindings.txt for details.
43 - resets: Must contain an entry for each entry in reset-names.
44 See ../reset/reset.txt for details.
45 - reset-names: Must include the following entries:
48 - epp: encoder pre-processor
51 - compatible: "nvidia,tegra<chip>-epp"
52 - reg: Physical base address and length of the controller's registers.
53 - interrupts: The interrupt outputs from the controller.
54 - clocks: Must contain one entry, for the module clock.
55 See ../clocks/clock-bindings.txt for details.
56 - resets: Must contain an entry for each entry in reset-names.
57 See ../reset/reset.txt for details.
58 - reset-names: Must include the following entries:
61 - isp: image signal processor
64 - compatible: "nvidia,tegra<chip>-isp"
65 - reg: Physical base address and length of the controller's registers.
66 - interrupts: The interrupt outputs from the controller.
67 - clocks: Must contain one entry, for the module clock.
68 See ../clocks/clock-bindings.txt for details.
69 - resets: Must contain an entry for each entry in reset-names.
70 See ../reset/reset.txt for details.
71 - reset-names: Must include the following entries:
74 - gr2d: 2D graphics engine
77 - compatible: "nvidia,tegra<chip>-gr2d"
78 - reg: Physical base address and length of the controller's registers.
79 - interrupts: The interrupt outputs from the controller.
80 - clocks: Must contain one entry, for the module clock.
81 See ../clocks/clock-bindings.txt for details.
82 - resets: Must contain an entry for each entry in reset-names.
83 See ../reset/reset.txt for details.
84 - reset-names: Must include the following entries:
87 - gr3d: 3D graphics engine
90 - compatible: "nvidia,tegra<chip>-gr3d"
91 - reg: Physical base address and length of the controller's registers.
92 - clocks: Must contain an entry for each entry in clock-names.
93 See ../clocks/clock-bindings.txt for details.
94 - clock-names: Must include the following entries:
95 (This property may be omitted if the only clock in the list is "3d")
97 This MUST be the first entry.
98 - 3d2 (Only required on SoCs with two 3D clocks)
99 - resets: Must contain an entry for each entry in reset-names.
100 See ../reset/reset.txt for details.
101 - reset-names: Must include the following entries:
103 - 3d2 (Only required on SoCs with two 3D clocks)
105 - dc: display controller
108 - compatible: "nvidia,tegra<chip>-dc"
109 - reg: Physical base address and length of the controller's registers.
110 - interrupts: The interrupt outputs from the controller.
111 - clocks: Must contain an entry for each entry in clock-names.
112 See ../clocks/clock-bindings.txt for details.
113 - clock-names: Must include the following entries:
115 This MUST be the first entry.
117 - resets: Must contain an entry for each entry in reset-names.
118 See ../reset/reset.txt for details.
119 - reset-names: Must include the following entries:
121 - nvidia,head: The number of the display controller head. This is used to
122 setup the various types of output to receive video data from the given
125 Each display controller node has a child node, named "rgb", that represents
126 the RGB output associated with the controller. It can take the following
128 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
129 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
130 - nvidia,edid: supplies a binary EDID blob
131 - nvidia,panel: phandle of a display panel
133 - hdmi: High Definition Multimedia Interface
136 - compatible: "nvidia,tegra<chip>-hdmi"
137 - reg: Physical base address and length of the controller's registers.
138 - interrupts: The interrupt outputs from the controller.
139 - vdd-supply: regulator for supply voltage
140 - pll-supply: regulator for PLL
141 - clocks: Must contain an entry for each entry in clock-names.
142 See ../clocks/clock-bindings.txt for details.
143 - clock-names: Must include the following entries:
145 This MUST be the first entry.
147 - resets: Must contain an entry for each entry in reset-names.
148 See ../reset/reset.txt for details.
149 - reset-names: Must include the following entries:
153 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
154 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
155 - nvidia,edid: supplies a binary EDID blob
156 - nvidia,panel: phandle of a display panel
158 - tvo: TV encoder output
161 - compatible: "nvidia,tegra<chip>-tvo"
162 - reg: Physical base address and length of the controller's registers.
163 - interrupts: The interrupt outputs from the controller.
164 - clocks: Must contain one entry, for the module clock.
165 See ../clocks/clock-bindings.txt for details.
167 - dsi: display serial interface
170 - compatible: "nvidia,tegra<chip>-dsi"
171 - reg: Physical base address and length of the controller's registers.
172 - clocks: Must contain an entry for each entry in clock-names.
173 See ../clocks/clock-bindings.txt for details.
174 - clock-names: Must include the following entries:
176 This MUST be the first entry.
179 - resets: Must contain an entry for each entry in reset-names.
180 See ../reset/reset.txt for details.
181 - reset-names: Must include the following entries:
183 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
184 which pads are used by this DSI output and need to be calibrated. See also
185 ../mipi/nvidia,tegra114-mipi.txt.
188 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
189 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
190 - nvidia,edid: supplies a binary EDID blob
191 - nvidia,panel: phandle of a display panel
199 compatible = "nvidia,tegra20-host1x", "simple-bus";
200 reg = <0x50000000 0x00024000>;
201 interrupts = <0 65 0x04 /* mpcore syncpt */
202 0 67 0x04>; /* mpcore general */
203 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
204 resets = <&tegra_car 28>;
205 reset-names = "host1x";
207 #address-cells = <1>;
210 ranges = <0x54000000 0x54000000 0x04000000>;
213 compatible = "nvidia,tegra20-mpe";
214 reg = <0x54040000 0x00040000>;
215 interrupts = <0 68 0x04>;
216 clocks = <&tegra_car TEGRA20_CLK_MPE>;
217 resets = <&tegra_car 60>;
222 compatible = "nvidia,tegra20-vi";
223 reg = <0x54080000 0x00040000>;
224 interrupts = <0 69 0x04>;
225 clocks = <&tegra_car TEGRA20_CLK_VI>;
226 resets = <&tegra_car 100>;
231 compatible = "nvidia,tegra20-epp";
232 reg = <0x540c0000 0x00040000>;
233 interrupts = <0 70 0x04>;
234 clocks = <&tegra_car TEGRA20_CLK_EPP>;
235 resets = <&tegra_car 19>;
240 compatible = "nvidia,tegra20-isp";
241 reg = <0x54100000 0x00040000>;
242 interrupts = <0 71 0x04>;
243 clocks = <&tegra_car TEGRA20_CLK_ISP>;
244 resets = <&tegra_car 23>;
249 compatible = "nvidia,tegra20-gr2d";
250 reg = <0x54140000 0x00040000>;
251 interrupts = <0 72 0x04>;
252 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
253 resets = <&tegra_car 21>;
258 compatible = "nvidia,tegra20-gr3d";
259 reg = <0x54180000 0x00040000>;
260 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
261 resets = <&tegra_car 24>;
266 compatible = "nvidia,tegra20-dc";
267 reg = <0x54200000 0x00040000>;
268 interrupts = <0 73 0x04>;
269 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
270 <&tegra_car TEGRA20_CLK_PLL_P>;
271 clock-names = "dc", "parent";
272 resets = <&tegra_car 27>;
281 compatible = "nvidia,tegra20-dc";
282 reg = <0x54240000 0x00040000>;
283 interrupts = <0 74 0x04>;
284 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
285 <&tegra_car TEGRA20_CLK_PLL_P>;
286 clock-names = "dc", "parent";
287 resets = <&tegra_car 26>;
296 compatible = "nvidia,tegra20-hdmi";
297 reg = <0x54280000 0x00040000>;
298 interrupts = <0 75 0x04>;
299 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
300 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
301 clock-names = "hdmi", "parent";
302 resets = <&tegra_car 51>;
303 reset-names = "hdmi";
308 compatible = "nvidia,tegra20-tvo";
309 reg = <0x542c0000 0x00040000>;
310 interrupts = <0 76 0x04>;
311 clocks = <&tegra_car TEGRA20_CLK_TVO>;
316 compatible = "nvidia,tegra20-dsi";
317 reg = <0x54300000 0x00040000>;
318 clocks = <&tegra_car TEGRA20_CLK_DSI>,
319 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
320 clock-names = "dsi", "parent";
321 resets = <&tegra_car 48>;