Documentation/devicetree/bindings/gpu/st,stih4xx.txt

   1 STMicroelectronics stih4xx platforms
   2
   3 - sti-vtg: video timing generator
   4   Required properties:
   5   - compatible: "st,vtg"
   6   - reg: Physical base address of the IP registers and length of memory mapped region.
   7   Optional properties:
   8   - interrupts : VTG interrupt number to the CPU.
   9   - st,slave: phandle on a slave vtg
  10
  11 - sti-vtac: video timing advanced inter dye communication Rx and TX
  12   Required properties:
  13   - compatible: "st,vtac-main" or "st,vtac-aux"
  14   - reg: Physical base address of the IP registers and length of memory mapped region.
  15   - clocks: from common clock binding: handle hardware IP needed clocks, the
  16     number of clocks may depend of the SoC type.
  17     See ../clocks/clock-bindings.txt for details.
  18   - clock-names: names of the clocks listed in clocks property in the same
  19     order.
  20
  21 - sti-display-subsystem: Master device for DRM sub-components
  22   This device must be the parent of all the sub-components and is responsible
  23   of bind them.
  24   Required properties:
  25   - compatible: "st,sti-display-subsystem"
  26   - ranges: to allow probing of subdevices
  27
  28 - sti-compositor: frame compositor engine
  29   must be a child of sti-display-subsystem
  30   Required properties:
  31   - compatible: "st,stih<chip>-compositor"
  32   - reg: Physical base address of the IP registers and length of memory mapped region.
  33   - clocks: from common clock binding: handle hardware IP needed clocks, the
  34     number of clocks may depend of the SoC type.
  35     See ../clocks/clock-bindings.txt for details.
  36   - clock-names: names of the clocks listed in clocks property in the same
  37     order.
  38   - resets: resets to be used by the device
  39     See ../reset/reset.txt for details.
  40   - reset-names: names of the resets listed in resets property in the same
  41     order.
  42   - st,vtg: phandle(s) on vtg device (main and aux) nodes.
  43
  44 - sti-tvout: video out hardware block
  45   must be a child of sti-display-subsystem
  46   Required properties:
  47   - compatible: "st,stih<chip>-tvout"
  48   - reg: Physical base address of the IP registers and length of memory mapped region.
  49   - reg-names: names of the mapped memory regions listed in regs property in
  50     the same order.
  51   - resets: resets to be used by the device
  52     See ../reset/reset.txt for details.
  53   - reset-names: names of the resets listed in resets property in the same
  54     order.
  55   - ranges: to allow probing of subdevices
  56
  57 - sti-hdmi: hdmi output block
  58   must be a child of sti-tvout
  59   Required properties:
  60   - compatible: "st,stih<chip>-hdmi";
  61   - reg: Physical base address of the IP registers and length of memory mapped region.
  62   - reg-names: names of the mapped memory regions listed in regs property in
  63     the same order.
  64   - interrupts : HDMI interrupt number to the CPU.
  65   - interrupt-names: name of the interrupts listed in interrupts property in
  66     the same order
  67   - clocks: from common clock binding: handle hardware IP needed clocks, the
  68     number of clocks may depend of the SoC type.
  69   - clock-names: names of the clocks listed in clocks property in the same
  70     order.
  71   - hdmi,hpd-gpio: gpio id to detect if an hdmi cable is plugged or not.
  72
  73 sti-hda:
  74   Required properties:
  75   must be a child of sti-tvout
  76   - compatible: "st,stih<chip>-hda"
  77   - reg: Physical base address of the IP registers and length of memory mapped region.
  78   - reg-names: names of the mapped memory regions listed in regs property in
  79     the same order.
  80   - clocks: from common clock binding: handle hardware IP needed clocks, the
  81     number of clocks may depend of the SoC type.
  82     See ../clocks/clock-bindings.txt for details.
  83   - clock-names: names of the clocks listed in clocks property in the same
  84     order.
  85
  86 Example:
  87
  88 / {
  89         ...
  90
  91         vtg_main_slave: sti-vtg-main-slave@fe85A800 {
  92                 compatible      = "st,vtg";
  93                 reg             = <0xfe85A800 0x300>;
  94                 interrupts      = <GIC_SPI 175 IRQ_TYPE_NONE>;
  95         };
  96
  97         vtg_main: sti-vtg-main-master@fd348000 {
  98                 compatible      = "st,vtg";
  99                 reg             = <0xfd348000 0x400>;
 100                 st,slave        = <&vtg_main_slave>;
 101         };
 102
 103         vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
 104                 compatible      = "st,vtg";
 105                 reg             = <0xfe858200 0x300>;
 106                 interrupts      = <GIC_SPI 176 IRQ_TYPE_NONE>;
 107         };
 108
 109         vtg_aux: sti-vtg-aux-master@fd348400 {
 110                 compatible      = "st,vtg";
 111                 reg             = <0xfd348400 0x400>;
 112                 st,slave        = <&vtg_aux_slave>;
 113         };
 114
 115
 116         sti-vtac-rx-main@fee82800 {
 117                 compatible      = "st,vtac-main";
 118                 reg             = <0xfee82800 0x200>;
 119                 clock-names     = "vtac";
 120                 clocks          = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
 121         };
 122
 123         sti-vtac-rx-aux@fee82a00 {
 124                 compatible      = "st,vtac-aux";
 125                 reg             = <0xfee82a00 0x200>;
 126                 clock-names     = "vtac";
 127                 clocks          = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
 128         };
 129
 130         sti-vtac-tx-main@fd349000 {
 131                 compatible      = "st,vtac-main";
 132                 reg             = <0xfd349000 0x200>, <0xfd320000 0x10000>;
 133                 clock-names     = "vtac";
 134                 clocks           = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
 135         };
 136
 137         sti-vtac-tx-aux@fd349200 {
 138                 compatible      = "st,vtac-aux";
 139                 reg             = <0xfd349200 0x200>, <0xfd320000 0x10000>;
 140                 clock-names     = "vtac";
 141                 clocks          = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
 142         };
 143
 144         sti-display-subsystem {
 145                 compatible = "st,sti-display-subsystem";
 146                 ranges;
 147
 148                 sti-compositor@fd340000 {
 149                         compatible      = "st,stih416-compositor";
 150                         reg             = <0xfd340000 0x1000>;
 151                         clock-names     = "compo_main", "compo_aux",
 152                                           "pix_main", "pix_aux";
 153                         clocks          = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
 154                                           <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
 155                         reset-names     = "compo-main", "compo-aux";
 156                         resets          = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
 157                         st,vtg          = <&vtg_main>, <&vtg_aux>;
 158                 };
 159
 160                 sti-tvout@fe000000 {
 161                         compatible      = "st,stih416-tvout";
 162                         reg             = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
 163                         reg-names       = "tvout-reg", "hda-reg", "syscfg";
 164                         reset-names     = "tvout";
 165                         resets          = <&softreset STIH416_HDTVOUT_SOFTRESET>;
 166                         ranges;
 167
 168                         sti-hdmi@fe85c000 {
 169                                 compatible      = "st,stih416-hdmi";
 170                                 reg             = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
 171                                 reg-names       = "hdmi-reg", "syscfg";
 172                                 interrupts      = <GIC_SPI 173 IRQ_TYPE_NONE>;
 173                                 interrupt-names = "irq";
 174                                 clock-names     = "pix", "tmds", "phy", "audio";
 175                                 clocks          = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
 176                                 hdmi,hpd-gpio   = <&PIO2 5>;
 177                         };
 178
 179                         sti-hda@fe85a000 {
 180                                 compatible      = "st,stih416-hda";
 181                                 reg             = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
 182                                 reg-names       = "hda-reg", "video-dacs-ctrl";
 183                                 clock-names     = "pix", "hddac";
 184                                 clocks          = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
 185                         };
 186                 };
 187         };
 188         ...
 189 };