Documentation/devicetree/bindings/video/exynos_dp.txt

   1 The Exynos display port interface should be configured based on
   2 the type of panel connected to it.
   3
   4 We use two nodes:
   5         -dp-controller node
   6         -dptx-phy node(defined inside dp-controller node)
   7
   8 For the DP-PHY initialization, we use the dptx-phy node.
   9 Required properties for dptx-phy:
  10         -reg:
  11                 Base address of DP PHY register.
  12         -samsung,enable-mask:
  13                 The bit-mask used to enable/disable DP PHY.
  14
  15 For the Panel initialization, we read data from dp-controller node.
  16 Required properties for dp-controller:
  17         -compatible:
  18                 should be "samsung,exynos5-dp".
  19         -reg:
  20                 physical base address of the controller and length
  21                 of memory mapped region.
  22         -interrupts:
  23                 interrupt combiner values.
  24         -clocks:
  25                 from common clock binding: handle to dp clock.
  26         -clock-names:
  27                 from common clock binding: Shall be "dp".
  28         -interrupt-parent:
  29                 phandle to Interrupt combiner node.
  30         -samsung,color-space:
  31                 input video data format.
  32                         COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
  33         -samsung,dynamic-range:
  34                 dynamic range for input video data.
  35                         VESA = 0, CEA = 1
  36         -samsung,ycbcr-coeff:
  37                 YCbCr co-efficients for input video.
  38                         COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
  39         -samsung,color-depth:
  40                 number of bits per colour component.
  41                         COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
  42         -samsung,link-rate:
  43                 link rate supported by the panel.
  44                         LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
  45         -samsung,lane-count:
  46                 number of lanes supported by the panel.
  47                         LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
  48
  49 Optional properties for dp-controller:
  50         -interlaced:
  51                 interlace scan mode.
  52                         Progressive if defined, Interlaced if not defined
  53         -vsync-active-high:
  54                 VSYNC polarity configuration.
  55                         High if defined, Low if not defined
  56         -hsync-active-high:
  57                 HSYNC polarity configuration.
  58                         High if defined, Low if not defined
  59
  60 Example:
  61
  62 SOC specific portion:
  63         dp-controller {
  64                 compatible = "samsung,exynos5-dp";
  65                 reg = <0x145b0000 0x10000>;
  66                 interrupts = <10 3>;
  67                 interrupt-parent = <&combiner>;
  68                 clocks = <&clock 342>;
  69                 clock-names = "dp";
  70
  71                 dptx-phy {
  72                         reg = <0x10040720>;
  73                         samsung,enable-mask = <1>;
  74                 };
  75
  76         };
  77
  78 Board Specific portion:
  79         dp-controller {
  80                 samsung,color-space = <0>;
  81                 samsung,dynamic-range = <0>;
  82                 samsung,ycbcr-coeff = <0>;
  83                 samsung,color-depth = <1>;
  84                 samsung,link-rate = <0x0a>;
  85                 samsung,lane-count = <4>;
  86         };