1 Device-Tree bindings for Samsung SoC display controller (FIMD)
3 FIMD (Fully Interactive Mobile Display) is the Display Controller for the
4 Samsung series of SoCs which transfers the image data from a video memory
5 buffer to an external LCD interface.
8 - compatible: value should be one of the following
9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
11 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
12 "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
13 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
14 "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
16 - reg: physical base address and length of the FIMD registers set.
18 - interrupt-parent: should be the phandle of the fimd controller's
19 parent interrupt controller.
21 - interrupts: should contain a list of all FIMD IP block interrupts in the
22 order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
23 format depends on the interrupt controller used.
25 - interrupt-names: should contain the interrupt names: "fifo", "vsync",
26 "lcd_sys", in the same order as they were listed in the interrupts
29 - pinctrl-0: pin control group to be used for this controller.
31 - pinctrl-names: must contain a "default" entry.
33 - clocks: must include clock specifiers corresponding to entries in the
36 - clock-names: list of clock names sorted in the same order as the clocks
37 property. Must contain "sclk_fimd" and "fimd".
40 - samsung,power-domain: a phandle to FIMD power domain node.
41 - samsung,invert-vden: video enable signal is inverted
42 - samsung,invert-vclk: video clock signal is inverted
43 - display-timings: timing settings for FIMD, as described in document [1].
44 Can be used in case timings cannot be provided otherwise
45 or to override timings provided by the panel.
46 - samsung,sysreg: handle to syscon used to control the system registers
47 - i80-if-timings: timing configuration for lcd i80 interface support.
48 - cs-setup: clock cycles for the active period of address signal is enabled
49 until chip select is enabled.
50 If not specified, the default value(0) will be used.
51 - wr-setup: clock cycles for the active period of CS signal is enabled until
52 write signal is enabled.
53 If not specified, the default value(0) will be used.
54 - wr-active: clock cycles for the active period of CS is enabled.
55 If not specified, the default value(1) will be used.
56 - wr-hold: clock cycles for the active period of CS is disabled until write
58 If not specified, the default value(0) will be used.
60 The parameters are defined as:
62 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
64 Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
67 Chip Select ???????????????|____________:____________:____________|??
68 | wr-setup+1 | | wr-hold+1 |
69 |<---------->| |<---------->|
70 Write Enable ????????????????????????????|____________|???????????????
73 Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
75 The device node can contain 'port' child nodes according to the bindings defined
76 in [2]. The following are properties specific to those nodes:
77 - reg: (required) port index, can be:
81 3 - for parallel output,
82 4 - for write-back interface
84 [1]: Documentation/devicetree/bindings/video/display-timing.txt
85 [2]: Documentation/devicetree/bindings/media/video-interfaces.txt
89 SoC specific DT entry:
92 compatible = "samsung,exynos4210-fimd";
93 interrupt-parent = <&combiner>;
94 reg = <0x11c00000 0x20000>;
95 interrupt-names = "fifo", "vsync", "lcd_sys";
96 interrupts = <11 0>, <11 1>, <11 2>;
97 clocks = <&clock 140>, <&clock 283>;
98 clock-names = "sclk_fimd", "fimd";
99 samsung,power-domain = <&pd_lcd0>;
103 Board specific DT entry:
106 pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
107 pinctrl-names = "default";