1 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
5 By: David Howells <dhowells@redhat.com>
6 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
10 (*) Abstract memory access model.
15 (*) What are memory barriers?
17 - Varieties of memory barrier.
18 - What may not be assumed about memory barriers?
19 - Data dependency barriers.
20 - Control dependencies.
21 - SMP barrier pairing.
22 - Examples of memory barrier sequences.
23 - Read memory barriers vs load speculation.
26 (*) Explicit kernel barriers.
29 - CPU memory barriers.
32 (*) Implicit kernel memory barriers.
35 - Interrupt disabling functions.
36 - Sleep and wake-up functions.
37 - Miscellaneous functions.
39 (*) Inter-CPU locking barrier effects.
41 - Locks vs memory accesses.
42 - Locks vs I/O accesses.
44 (*) Where are memory barriers needed?
46 - Interprocessor interaction.
51 (*) Kernel I/O barrier effects.
53 (*) Assumed minimum execution ordering model.
55 (*) The effects of the cpu cache.
58 - Cache coherency vs DMA.
59 - Cache coherency vs MMIO.
61 (*) The things CPUs get up to.
63 - And then there's the Alpha.
72 ============================
73 ABSTRACT MEMORY ACCESS MODEL
74 ============================
76 Consider the following abstract model of the system:
81 +-------+ : +--------+ : +-------+
84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
87 +-------+ : +--------+ : +-------+
95 +---------->| Device |<----------+
101 Each CPU executes a program that generates memory access operations. In the
102 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
103 perform the memory operations in any order it likes, provided program causality
104 appears to be maintained. Similarly, the compiler may also arrange the
105 instructions it emits in any order it likes, provided it doesn't affect the
106 apparent operation of the program.
108 So in the above diagram, the effects of the memory operations performed by a
109 CPU are perceived by the rest of the system as the operations cross the
110 interface between the CPU and rest of the system (the dotted lines).
113 For example, consider the following sequence of events:
116 =============== ===============
121 The set of accesses as seen by the memory system in the middle can be arranged
122 in 24 different combinations:
124 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
125 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
126 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
127 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
128 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
129 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
130 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
134 and can thus result in four different combinations of values:
142 Furthermore, the stores committed by a CPU to the memory system may not be
143 perceived by the loads made by another CPU in the same order as the stores were
147 As a further example, consider this sequence of events:
150 =============== ===============
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
155 There is an obvious data dependency here, as the value loaded into D depends on
156 the address retrieved from P by CPU 2. At the end of the sequence, any of the
157 following results are possible:
159 (Q == &A) and (D == 1)
160 (Q == &B) and (D == 2)
161 (Q == &B) and (D == 4)
163 Note that CPU 2 will never try and load C into D because the CPU will load P
164 into Q before issuing the load of *Q.
170 Some devices present their control interfaces as collections of memory
171 locations, but the order in which the control registers are accessed is very
172 important. For instance, imagine an ethernet card with a set of internal
173 registers that are accessed through an address port register (A) and a data
174 port register (D). To read internal register 5, the following code might then
180 but this might show up as either of the following two sequences:
182 STORE *A = 5, x = LOAD *D
183 x = LOAD *D, STORE *A = 5
185 the second of which will almost certainly result in a malfunction, since it set
186 the address _after_ attempting to read the register.
192 There are some minimal guarantees that may be expected of a CPU:
194 (*) On any given CPU, dependent memory accesses will be issued in order, with
195 respect to itself. This means that for:
197 ACCESS_ONCE(Q) = P; smp_read_barrier_depends(); D = ACCESS_ONCE(*Q);
199 the CPU will issue the following memory operations:
201 Q = LOAD P, D = LOAD *Q
203 and always in that order. On most systems, smp_read_barrier_depends()
204 does nothing, but it is required for DEC Alpha. The ACCESS_ONCE()
205 is required to prevent compiler mischief. Please note that you
206 should normally use something like rcu_dereference() instead of
207 open-coding smp_read_barrier_depends().
209 (*) Overlapping loads and stores within a particular CPU will appear to be
210 ordered within that CPU. This means that for:
212 a = ACCESS_ONCE(*X); ACCESS_ONCE(*X) = b;
214 the CPU will only issue the following sequence of memory operations:
216 a = LOAD *X, STORE *X = b
220 ACCESS_ONCE(*X) = c; d = ACCESS_ONCE(*X);
222 the CPU will only issue:
224 STORE *X = c, d = LOAD *X
226 (Loads and stores overlap if they are targeted at overlapping pieces of
229 And there are a number of things that _must_ or _must_not_ be assumed:
231 (*) It _must_not_ be assumed that the compiler will do what you want with
232 memory references that are not protected by ACCESS_ONCE(). Without
233 ACCESS_ONCE(), the compiler is within its rights to do all sorts
234 of "creative" transformations, which are covered in the Compiler
237 (*) It _must_not_ be assumed that independent loads and stores will be issued
238 in the order given. This means that for:
240 X = *A; Y = *B; *D = Z;
242 we may get any of the following sequences:
244 X = LOAD *A, Y = LOAD *B, STORE *D = Z
245 X = LOAD *A, STORE *D = Z, Y = LOAD *B
246 Y = LOAD *B, X = LOAD *A, STORE *D = Z
247 Y = LOAD *B, STORE *D = Z, X = LOAD *A
248 STORE *D = Z, X = LOAD *A, Y = LOAD *B
249 STORE *D = Z, Y = LOAD *B, X = LOAD *A
251 (*) It _must_ be assumed that overlapping memory accesses may be merged or
252 discarded. This means that for:
254 X = *A; Y = *(A + 4);
256 we may get any one of the following sequences:
258 X = LOAD *A; Y = LOAD *(A + 4);
259 Y = LOAD *(A + 4); X = LOAD *A;
260 {X, Y} = LOAD {*A, *(A + 4) };
264 *A = X; *(A + 4) = Y;
268 STORE *A = X; STORE *(A + 4) = Y;
269 STORE *(A + 4) = Y; STORE *A = X;
270 STORE {*A, *(A + 4) } = {X, Y};
273 =========================
274 WHAT ARE MEMORY BARRIERS?
275 =========================
277 As can be seen above, independent memory operations are effectively performed
278 in random order, but this can be a problem for CPU-CPU interaction and for I/O.
279 What is required is some way of intervening to instruct the compiler and the
280 CPU to restrict the order.
282 Memory barriers are such interventions. They impose a perceived partial
283 ordering over the memory operations on either side of the barrier.
285 Such enforcement is important because the CPUs and other devices in a system
286 can use a variety of tricks to improve performance, including reordering,
287 deferral and combination of memory operations; speculative loads; speculative
288 branch prediction and various types of caching. Memory barriers are used to
289 override or suppress these tricks, allowing the code to sanely control the
290 interaction of multiple CPUs and/or devices.
293 VARIETIES OF MEMORY BARRIER
294 ---------------------------
296 Memory barriers come in four basic varieties:
298 (1) Write (or store) memory barriers.
300 A write memory barrier gives a guarantee that all the STORE operations
301 specified before the barrier will appear to happen before all the STORE
302 operations specified after the barrier with respect to the other
303 components of the system.
305 A write barrier is a partial ordering on stores only; it is not required
306 to have any effect on loads.
308 A CPU can be viewed as committing a sequence of store operations to the
309 memory system as time progresses. All stores before a write barrier will
310 occur in the sequence _before_ all the stores after the write barrier.
312 [!] Note that write barriers should normally be paired with read or data
313 dependency barriers; see the "SMP barrier pairing" subsection.
316 (2) Data dependency barriers.
318 A data dependency barrier is a weaker form of read barrier. In the case
319 where two loads are performed such that the second depends on the result
320 of the first (eg: the first load retrieves the address to which the second
321 load will be directed), a data dependency barrier would be required to
322 make sure that the target of the second load is updated before the address
323 obtained by the first load is accessed.
325 A data dependency barrier is a partial ordering on interdependent loads
326 only; it is not required to have any effect on stores, independent loads
327 or overlapping loads.
329 As mentioned in (1), the other CPUs in the system can be viewed as
330 committing sequences of stores to the memory system that the CPU being
331 considered can then perceive. A data dependency barrier issued by the CPU
332 under consideration guarantees that for any load preceding it, if that
333 load touches one of a sequence of stores from another CPU, then by the
334 time the barrier completes, the effects of all the stores prior to that
335 touched by the load will be perceptible to any loads issued after the data
338 See the "Examples of memory barrier sequences" subsection for diagrams
339 showing the ordering constraints.
341 [!] Note that the first load really has to have a _data_ dependency and
342 not a control dependency. If the address for the second load is dependent
343 on the first load, but the dependency is through a conditional rather than
344 actually loading the address itself, then it's a _control_ dependency and
345 a full read barrier or better is required. See the "Control dependencies"
346 subsection for more information.
348 [!] Note that data dependency barriers should normally be paired with
349 write barriers; see the "SMP barrier pairing" subsection.
352 (3) Read (or load) memory barriers.
354 A read barrier is a data dependency barrier plus a guarantee that all the
355 LOAD operations specified before the barrier will appear to happen before
356 all the LOAD operations specified after the barrier with respect to the
357 other components of the system.
359 A read barrier is a partial ordering on loads only; it is not required to
360 have any effect on stores.
362 Read memory barriers imply data dependency barriers, and so can substitute
365 [!] Note that read barriers should normally be paired with write barriers;
366 see the "SMP barrier pairing" subsection.
369 (4) General memory barriers.
371 A general memory barrier gives a guarantee that all the LOAD and STORE
372 operations specified before the barrier will appear to happen before all
373 the LOAD and STORE operations specified after the barrier with respect to
374 the other components of the system.
376 A general memory barrier is a partial ordering over both loads and stores.
378 General memory barriers imply both read and write memory barriers, and so
379 can substitute for either.
382 And a couple of implicit varieties:
384 (5) ACQUIRE operations.
386 This acts as a one-way permeable barrier. It guarantees that all memory
387 operations after the ACQUIRE operation will appear to happen after the
388 ACQUIRE operation with respect to the other components of the system.
389 ACQUIRE operations include LOCK operations and smp_load_acquire()
392 Memory operations that occur before an ACQUIRE operation may appear to
393 happen after it completes.
395 An ACQUIRE operation should almost always be paired with a RELEASE
399 (6) RELEASE operations.
401 This also acts as a one-way permeable barrier. It guarantees that all
402 memory operations before the RELEASE operation will appear to happen
403 before the RELEASE operation with respect to the other components of the
404 system. RELEASE operations include UNLOCK operations and
405 smp_store_release() operations.
407 Memory operations that occur after a RELEASE operation may appear to
408 happen before it completes.
410 The use of ACQUIRE and RELEASE operations generally precludes the need
411 for other sorts of memory barrier (but note the exceptions mentioned in
412 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
413 pair is -not- guaranteed to act as a full memory barrier. However, after
414 an ACQUIRE on a given variable, all memory accesses preceding any prior
415 RELEASE on that same variable are guaranteed to be visible. In other
416 words, within a given variable's critical section, all accesses of all
417 previous critical sections for that variable are guaranteed to have
420 This means that ACQUIRE acts as a minimal "acquire" operation and
421 RELEASE acts as a minimal "release" operation.
424 Memory barriers are only required where there's a possibility of interaction
425 between two CPUs or between a CPU and a device. If it can be guaranteed that
426 there won't be any such interaction in any particular piece of code, then
427 memory barriers are unnecessary in that piece of code.
430 Note that these are the _minimum_ guarantees. Different architectures may give
431 more substantial guarantees, but they may _not_ be relied upon outside of arch
435 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
436 ----------------------------------------------
438 There are certain things that the Linux kernel memory barriers do not guarantee:
440 (*) There is no guarantee that any of the memory accesses specified before a
441 memory barrier will be _complete_ by the completion of a memory barrier
442 instruction; the barrier can be considered to draw a line in that CPU's
443 access queue that accesses of the appropriate type may not cross.
445 (*) There is no guarantee that issuing a memory barrier on one CPU will have
446 any direct effect on another CPU or any other hardware in the system. The
447 indirect effect will be the order in which the second CPU sees the effects
448 of the first CPU's accesses occur, but see the next point:
450 (*) There is no guarantee that a CPU will see the correct order of effects
451 from a second CPU's accesses, even _if_ the second CPU uses a memory
452 barrier, unless the first CPU _also_ uses a matching memory barrier (see
453 the subsection on "SMP Barrier Pairing").
455 (*) There is no guarantee that some intervening piece of off-the-CPU
456 hardware[*] will not reorder the memory accesses. CPU cache coherency
457 mechanisms should propagate the indirect effects of a memory barrier
458 between CPUs, but might not do so in order.
460 [*] For information on bus mastering DMA and coherency please read:
462 Documentation/PCI/pci.txt
463 Documentation/DMA-API-HOWTO.txt
464 Documentation/DMA-API.txt
467 DATA DEPENDENCY BARRIERS
468 ------------------------
470 The usage requirements of data dependency barriers are a little subtle, and
471 it's not always obvious that they're needed. To illustrate, consider the
472 following sequence of events:
475 =============== ===============
476 { A == 1, B == 2, C = 3, P == &A, Q == &C }
483 There's a clear data dependency here, and it would seem that by the end of the
484 sequence, Q must be either &A or &B, and that:
486 (Q == &A) implies (D == 1)
487 (Q == &B) implies (D == 4)
489 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
490 leading to the following situation:
492 (Q == &B) and (D == 2) ????
494 Whilst this may seem like a failure of coherency or causality maintenance, it
495 isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
498 To deal with this, a data dependency barrier or better must be inserted
499 between the address load and the data load:
502 =============== ===============
503 { A == 1, B == 2, C = 3, P == &A, Q == &C }
508 <data dependency barrier>
511 This enforces the occurrence of one of the two implications, and prevents the
512 third possibility from arising.
514 [!] Note that this extremely counterintuitive situation arises most easily on
515 machines with split caches, so that, for example, one cache bank processes
516 even-numbered cache lines and the other bank processes odd-numbered cache
517 lines. The pointer P might be stored in an odd-numbered cache line, and the
518 variable B might be stored in an even-numbered cache line. Then, if the
519 even-numbered bank of the reading CPU's cache is extremely busy while the
520 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
521 but the old value of the variable B (2).
524 Another example of where data dependency barriers might be required is where a
525 number is read from memory and then used to calculate the index for an array
529 =============== ===============
530 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
535 <data dependency barrier>
539 The data dependency barrier is very important to the RCU system,
540 for example. See rcu_assign_pointer() and rcu_dereference() in
541 include/linux/rcupdate.h. This permits the current target of an RCU'd
542 pointer to be replaced with a new modified target, without the replacement
543 target appearing to be incompletely initialised.
545 See also the subsection on "Cache Coherency" for a more thorough example.
551 A control dependency requires a full read memory barrier, not simply a data
552 dependency barrier to make it work correctly. Consider the following bit of
557 <data dependency barrier> /* BUG: No data dependency!!! */
561 This will not have the desired effect because there is no actual data
562 dependency, but rather a control dependency that the CPU may short-circuit
563 by attempting to predict the outcome in advance, so that other CPUs see
564 the load from b as having happened before the load from a. In such a
565 case what's actually required is:
573 However, stores are not speculated. This means that ordering -is- provided
574 in the following example:
581 Please note that ACCESS_ONCE() is not optional! Without the
582 ACCESS_ONCE(), might combine the load from 'a' with other loads from
583 'a', and the store to 'b' with other stores to 'b', with possible highly
584 counterintuitive effects on ordering.
586 Worse yet, if the compiler is able to prove (say) that the value of
587 variable 'a' is always non-zero, it would be well within its rights
588 to optimize the original example by eliminating the "if" statement
592 b = p; /* BUG: Compiler and CPU can both reorder!!! */
594 So don't leave out the ACCESS_ONCE().
596 It is tempting to try to enforce ordering on identical stores on both
597 branches of the "if" statement as follows:
610 Unfortunately, current compilers will transform this as follows at high
615 ACCESS_ONCE(b) = p; /* BUG: No ordering vs. load from a!!! */
617 /* ACCESS_ONCE(b) = p; -- moved up, BUG!!! */
620 /* ACCESS_ONCE(b) = p; -- moved up, BUG!!! */
624 Now there is no conditional between the load from 'a' and the store to
625 'b', which means that the CPU is within its rights to reorder them:
626 The conditional is absolutely required, and must be present in the
627 assembly code even after all compiler optimizations have been applied.
628 Therefore, if you need ordering in this example, you need explicit
629 memory barriers, for example, smp_store_release():
633 smp_store_release(&b, p);
636 smp_store_release(&b, p);
640 In contrast, without explicit memory barriers, two-legged-if control
641 ordering is guaranteed only when the stores differ, for example:
652 The initial ACCESS_ONCE() is still required to prevent the compiler from
653 proving the value of 'a'.
655 In addition, you need to be careful what you do with the local variable 'q',
656 otherwise the compiler might be able to guess the value and again remove
657 the needed conditional. For example:
668 If MAX is defined to be 1, then the compiler knows that (q % MAX) is
669 equal to zero, in which case the compiler is within its rights to
670 transform the above code into the following:
676 Given this transformation, the CPU is not required to respect the ordering
677 between the load from variable 'a' and the store to variable 'b'. It is
678 tempting to add a barrier(), but this does not help. The conditional
679 is gone, and the barrier won't bring it back. Therefore, if you are
680 relying on this ordering, you should make sure that MAX is greater than
681 one, perhaps as follows:
684 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
693 Please note once again that the stores to 'b' differ. If they were
694 identical, as noted earlier, the compiler could pull this store outside
695 of the 'if' statement.
697 You must also be careful not to rely too much on boolean short-circuit
698 evaluation. Consider this example:
704 Because the second condition is always true, the compiler can transform
705 this example as following, defeating control dependency:
710 This example underscores the need to ensure that the compiler cannot
711 out-guess your code. More generally, although ACCESS_ONCE() does force
712 the compiler to actually emit code for a given load, it does not force
713 the compiler to use the results.
715 Finally, control dependencies do -not- provide transitivity. This is
716 demonstrated by two related examples, with the initial values of
717 x and y both being zero:
720 ===================== =====================
721 r1 = ACCESS_ONCE(x); r2 = ACCESS_ONCE(y);
722 if (r1 > 0) if (r2 > 0)
723 ACCESS_ONCE(y) = 1; ACCESS_ONCE(x) = 1;
725 assert(!(r1 == 1 && r2 == 1));
727 The above two-CPU example will never trigger the assert(). However,
728 if control dependencies guaranteed transitivity (which they do not),
729 then adding the following CPU would guarantee a related assertion:
732 =====================
735 assert(!(r1 == 2 && r2 == 1 && x == 2)); /* FAILS!!! */
737 But because control dependencies do -not- provide transitivity, the above
738 assertion can fail after the combined three-CPU example completes. If you
739 need the three-CPU example to provide ordering, you will need smp_mb()
740 between the loads and stores in the CPU 0 and CPU 1 code fragments,
741 that is, just before or just after the "if" statements.
743 These two examples are the LB and WWC litmus tests from this paper:
744 http://www.cl.cam.ac.uk/users/pes20/ppc-supplemental/test6.pdf and this
745 site: https://www.cl.cam.ac.uk/~pes20/ppcmem/index.html.
749 (*) Control dependencies can order prior loads against later stores.
750 However, they do -not- guarantee any other sort of ordering:
751 Not prior loads against later loads, nor prior stores against
752 later anything. If you need these other forms of ordering,
753 use smb_rmb(), smp_wmb(), or, in the case of prior stores and
754 later loads, smp_mb().
756 (*) If both legs of the "if" statement begin with identical stores
757 to the same variable, a barrier() statement is required at the
758 beginning of each leg of the "if" statement.
760 (*) Control dependencies require at least one run-time conditional
761 between the prior load and the subsequent store, and this
762 conditional must involve the prior load. If the compiler
763 is able to optimize the conditional away, it will have also
764 optimized away the ordering. Careful use of ACCESS_ONCE() can
765 help to preserve the needed conditional.
767 (*) Control dependencies require that the compiler avoid reordering the
768 dependency into nonexistence. Careful use of ACCESS_ONCE() or
769 barrier() can help to preserve your control dependency. Please
770 see the Compiler Barrier section for more information.
772 (*) Control dependencies do -not- provide transitivity. If you
773 need transitivity, use smp_mb().
779 When dealing with CPU-CPU interactions, certain types of memory barrier should
780 always be paired. A lack of appropriate pairing is almost certainly an error.
782 General barriers pair with each other, though they also pair with
783 most other types of barriers, albeit without transitivity. An acquire
784 barrier pairs with a release barrier, but both may also pair with other
785 barriers, including of course general barriers. A write barrier pairs
786 with a data dependency barrier, an acquire barrier, a release barrier,
787 a read barrier, or a general barrier. Similarly a read barrier or a
788 data dependency barrier pairs with a write barrier, an acquire barrier,
789 a release barrier, or a general barrier:
792 =============== ===============
795 ACCESS_ONCE(b) = 2; x = ACCESS_ONCE(b);
802 =============== ===============================
805 ACCESS_ONCE(b) = &a; x = ACCESS_ONCE(b);
806 <data dependency barrier>
809 Basically, the read barrier always has to be there, even though it can be of
812 [!] Note that the stores before the write barrier would normally be expected to
813 match the loads after the read barrier or the data dependency barrier, and vice
817 =================== ===================
818 ACCESS_ONCE(a) = 1; }---- --->{ v = ACCESS_ONCE(c);
819 ACCESS_ONCE(b) = 2; } \ / { w = ACCESS_ONCE(d);
820 <write barrier> \ <read barrier>
821 ACCESS_ONCE(c) = 3; } / \ { x = ACCESS_ONCE(a);
822 ACCESS_ONCE(d) = 4; }---- --->{ y = ACCESS_ONCE(b);
825 EXAMPLES OF MEMORY BARRIER SEQUENCES
826 ------------------------------------
828 Firstly, write barriers act as partial orderings on store operations.
829 Consider the following sequence of events:
832 =======================
840 This sequence of events is committed to the memory coherence system in an order
841 that the rest of the system might perceive as the unordered set of { STORE A,
842 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
847 | |------>| C=3 | } /\
848 | | : +------+ }----- \ -----> Events perceptible to
849 | | : | A=1 | } \/ the rest of the system
851 | CPU 1 | : | B=2 | }
853 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
854 | | +------+ } requires all stores prior to the
855 | | : | E=5 | } barrier to be committed before
856 | | : +------+ } further stores may take place
861 | Sequence in which stores are committed to the
862 | memory system by CPU 1
866 Secondly, data dependency barriers act as partial orderings on data-dependent
867 loads. Consider the following sequence of events:
870 ======================= =======================
871 { B = 7; X = 9; Y = 8; C = &Y }
876 STORE D = 4 LOAD C (gets &B)
879 Without intervention, CPU 2 may perceive the events on CPU 1 in some
880 effectively random order, despite the write barrier issued by CPU 1:
883 | | +------+ +-------+ | Sequence of update
884 | |------>| B=2 |----- --->| Y->8 | | of perception on
885 | | : +------+ \ +-------+ | CPU 2
886 | CPU 1 | : | A=1 | \ --->| C->&Y | V
887 | | +------+ | +-------+
888 | | wwwwwwwwwwwwwwww | : :
890 | | : | C=&B |--- | : : +-------+
891 | | : +------+ \ | +-------+ | |
892 | |------>| D=4 | ----------->| C->&B |------>| |
893 | | +------+ | +-------+ | |
894 +-------+ : : | : : | |
898 Apparently incorrect ---> | | B->7 |------>| |
899 perception of B (!) | +-------+ | |
902 The load of X holds ---> \ | X->9 |------>| |
903 up the maintenance \ +-------+ | |
904 of coherence of B ----->| B->2 | +-------+
909 In the above example, CPU 2 perceives that B is 7, despite the load of *C
910 (which would be B) coming after the LOAD of C.
912 If, however, a data dependency barrier were to be placed between the load of C
913 and the load of *C (ie: B) on CPU 2:
916 ======================= =======================
917 { B = 7; X = 9; Y = 8; C = &Y }
922 STORE D = 4 LOAD C (gets &B)
923 <data dependency barrier>
926 then the following will occur:
929 | | +------+ +-------+
930 | |------>| B=2 |----- --->| Y->8 |
931 | | : +------+ \ +-------+
932 | CPU 1 | : | A=1 | \ --->| C->&Y |
933 | | +------+ | +-------+
934 | | wwwwwwwwwwwwwwww | : :
936 | | : | C=&B |--- | : : +-------+
937 | | : +------+ \ | +-------+ | |
938 | |------>| D=4 | ----------->| C->&B |------>| |
939 | | +------+ | +-------+ | |
940 +-------+ : : | : : | |
946 Makes sure all effects ---> \ ddddddddddddddddd | |
947 prior to the store of C \ +-------+ | |
948 are perceptible to ----->| B->2 |------>| |
949 subsequent loads +-------+ | |
953 And thirdly, a read barrier acts as a partial order on loads. Consider the
954 following sequence of events:
957 ======================= =======================
965 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
966 some effectively random order, despite the write barrier issued by CPU 1:
969 | | +------+ +-------+
970 | |------>| A=1 |------ --->| A->0 |
971 | | +------+ \ +-------+
972 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
973 | | +------+ | +-------+
974 | |------>| B=2 |--- | : :
975 | | +------+ \ | : : +-------+
976 +-------+ : : \ | +-------+ | |
977 ---------->| B->2 |------>| |
978 | +-------+ | CPU 2 |
989 If, however, a read barrier were to be placed between the load of B and the
993 ======================= =======================
1002 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1006 | | +------+ +-------+
1007 | |------>| A=1 |------ --->| A->0 |
1008 | | +------+ \ +-------+
1009 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1010 | | +------+ | +-------+
1011 | |------>| B=2 |--- | : :
1012 | | +------+ \ | : : +-------+
1013 +-------+ : : \ | +-------+ | |
1014 ---------->| B->2 |------>| |
1015 | +-------+ | CPU 2 |
1018 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1019 barrier causes all effects \ +-------+ | |
1020 prior to the storage of B ---->| A->1 |------>| |
1021 to be perceptible to CPU 2 +-------+ | |
1025 To illustrate this more completely, consider what could happen if the code
1026 contained a load of A either side of the read barrier:
1029 ======================= =======================
1035 LOAD A [first load of A]
1037 LOAD A [second load of A]
1039 Even though the two loads of A both occur after the load of B, they may both
1040 come up with different values:
1043 | | +------+ +-------+
1044 | |------>| A=1 |------ --->| A->0 |
1045 | | +------+ \ +-------+
1046 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1047 | | +------+ | +-------+
1048 | |------>| B=2 |--- | : :
1049 | | +------+ \ | : : +-------+
1050 +-------+ : : \ | +-------+ | |
1051 ---------->| B->2 |------>| |
1052 | +-------+ | CPU 2 |
1056 | | A->0 |------>| 1st |
1058 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1059 barrier causes all effects \ +-------+ | |
1060 prior to the storage of B ---->| A->1 |------>| 2nd |
1061 to be perceptible to CPU 2 +-------+ | |
1065 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1066 before the read barrier completes anyway:
1069 | | +------+ +-------+
1070 | |------>| A=1 |------ --->| A->0 |
1071 | | +------+ \ +-------+
1072 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1073 | | +------+ | +-------+
1074 | |------>| B=2 |--- | : :
1075 | | +------+ \ | : : +-------+
1076 +-------+ : : \ | +-------+ | |
1077 ---------->| B->2 |------>| |
1078 | +-------+ | CPU 2 |
1082 ---->| A->1 |------>| 1st |
1084 rrrrrrrrrrrrrrrrr | |
1086 | A->1 |------>| 2nd |
1091 The guarantee is that the second load will always come up with A == 1 if the
1092 load of B came up with B == 2. No such guarantee exists for the first load of
1093 A; that may come up with either A == 0 or A == 1.
1096 READ MEMORY BARRIERS VS LOAD SPECULATION
1097 ----------------------------------------
1099 Many CPUs speculate with loads: that is they see that they will need to load an
1100 item from memory, and they find a time where they're not using the bus for any
1101 other loads, and so do the load in advance - even though they haven't actually
1102 got to that point in the instruction execution flow yet. This permits the
1103 actual load instruction to potentially complete immediately because the CPU
1104 already has the value to hand.
1106 It may turn out that the CPU didn't actually need the value - perhaps because a
1107 branch circumvented the load - in which case it can discard the value or just
1108 cache it for later use.
1113 ======================= =======================
1115 DIVIDE } Divide instructions generally
1116 DIVIDE } take a long time to perform
1119 Which might appear as this:
1123 --->| B->2 |------>| |
1127 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1128 division speculates on the +-------+ ~ | |
1132 Once the divisions are complete --> : : ~-->| |
1133 the CPU can then perform the : : | |
1134 LOAD with immediate effect : : +-------+
1137 Placing a read barrier or a data dependency barrier just before the second
1141 ======================= =======================
1148 will force any value speculatively obtained to be reconsidered to an extent
1149 dependent on the type of barrier used. If there was no change made to the
1150 speculated memory location, then the speculated value will just be used:
1154 --->| B->2 |------>| |
1158 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1159 division speculates on the +-------+ ~ | |
1164 rrrrrrrrrrrrrrrr~ | |
1171 but if there was an update or an invalidation from another CPU pending, then
1172 the speculation will be cancelled and the value reloaded:
1176 --->| B->2 |------>| |
1180 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1181 division speculates on the +-------+ ~ | |
1186 rrrrrrrrrrrrrrrrr | |
1188 The speculation is discarded ---> --->| A->1 |------>| |
1189 and an updated value is +-------+ | |
1190 retrieved : : +-------+
1196 Transitivity is a deeply intuitive notion about ordering that is not
1197 always provided by real computer systems. The following example
1198 demonstrates transitivity (also called "cumulativity"):
1201 ======================= ======================= =======================
1203 STORE X=1 LOAD X STORE Y=1
1204 <general barrier> <general barrier>
1207 Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
1208 This indicates that CPU 2's load from X in some sense follows CPU 1's
1209 store to X and that CPU 2's load from Y in some sense preceded CPU 3's
1210 store to Y. The question is then "Can CPU 3's load from X return 0?"
1212 Because CPU 2's load from X in some sense came after CPU 1's store, it
1213 is natural to expect that CPU 3's load from X must therefore return 1.
1214 This expectation is an example of transitivity: if a load executing on
1215 CPU A follows a load from the same variable executing on CPU B, then
1216 CPU A's load must either return the same value that CPU B's load did,
1217 or must return some later value.
1219 In the Linux kernel, use of general memory barriers guarantees
1220 transitivity. Therefore, in the above example, if CPU 2's load from X
1221 returns 1 and its load from Y returns 0, then CPU 3's load from X must
1224 However, transitivity is -not- guaranteed for read or write barriers.
1225 For example, suppose that CPU 2's general barrier in the above example
1226 is changed to a read barrier as shown below:
1229 ======================= ======================= =======================
1231 STORE X=1 LOAD X STORE Y=1
1232 <read barrier> <general barrier>
1235 This substitution destroys transitivity: in this example, it is perfectly
1236 legal for CPU 2's load from X to return 1, its load from Y to return 0,
1237 and CPU 3's load from X to return 0.
1239 The key point is that although CPU 2's read barrier orders its pair
1240 of loads, it does not guarantee to order CPU 1's store. Therefore, if
1241 this example runs on a system where CPUs 1 and 2 share a store buffer
1242 or a level of cache, CPU 2 might have early access to CPU 1's writes.
1243 General barriers are therefore required to ensure that all CPUs agree
1244 on the combined order of CPU 1's and CPU 2's accesses.
1246 To reiterate, if your code requires transitivity, use general barriers
1250 ========================
1251 EXPLICIT KERNEL BARRIERS
1252 ========================
1254 The Linux kernel has a variety of different barriers that act at different
1257 (*) Compiler barrier.
1259 (*) CPU memory barriers.
1261 (*) MMIO write barrier.
1267 The Linux kernel has an explicit compiler barrier function that prevents the
1268 compiler from moving the memory accesses either side of it to the other side:
1272 This is a general barrier -- there are no read-read or write-write variants
1273 of barrier(). However, ACCESS_ONCE() can be thought of as a weak form
1274 for barrier() that affects only the specific accesses flagged by the
1277 The barrier() function has the following effects:
1279 (*) Prevents the compiler from reordering accesses following the
1280 barrier() to precede any accesses preceding the barrier().
1281 One example use for this property is to ease communication between
1282 interrupt-handler code and the code that was interrupted.
1284 (*) Within a loop, forces the compiler to load the variables used
1285 in that loop's conditional on each pass through that loop.
1287 The ACCESS_ONCE() function can prevent any number of optimizations that,
1288 while perfectly safe in single-threaded code, can be fatal in concurrent
1289 code. Here are some examples of these sorts of optimizations:
1291 (*) The compiler is within its rights to reorder loads and stores
1292 to the same variable, and in some cases, the CPU is within its
1293 rights to reorder loads to the same variable. This means that
1299 Might result in an older value of x stored in a[1] than in a[0].
1300 Prevent both the compiler and the CPU from doing this as follows:
1302 a[0] = ACCESS_ONCE(x);
1303 a[1] = ACCESS_ONCE(x);
1305 In short, ACCESS_ONCE() provides cache coherence for accesses from
1306 multiple CPUs to a single variable.
1308 (*) The compiler is within its rights to merge successive loads from
1309 the same variable. Such merging can cause the compiler to "optimize"
1313 do_something_with(tmp);
1315 into the following code, which, although in some sense legitimate
1316 for single-threaded code, is almost certainly not what the developer
1321 do_something_with(tmp);
1323 Use ACCESS_ONCE() to prevent the compiler from doing this to you:
1325 while (tmp = ACCESS_ONCE(a))
1326 do_something_with(tmp);
1328 (*) The compiler is within its rights to reload a variable, for example,
1329 in cases where high register pressure prevents the compiler from
1330 keeping all data of interest in registers. The compiler might
1331 therefore optimize the variable 'tmp' out of our previous example:
1334 do_something_with(tmp);
1336 This could result in the following code, which is perfectly safe in
1337 single-threaded code, but can be fatal in concurrent code:
1340 do_something_with(a);
1342 For example, the optimized version of this code could result in
1343 passing a zero to do_something_with() in the case where the variable
1344 a was modified by some other CPU between the "while" statement and
1345 the call to do_something_with().
1347 Again, use ACCESS_ONCE() to prevent the compiler from doing this:
1349 while (tmp = ACCESS_ONCE(a))
1350 do_something_with(tmp);
1352 Note that if the compiler runs short of registers, it might save
1353 tmp onto the stack. The overhead of this saving and later restoring
1354 is why compilers reload variables. Doing so is perfectly safe for
1355 single-threaded code, so you need to tell the compiler about cases
1356 where it is not safe.
1358 (*) The compiler is within its rights to omit a load entirely if it knows
1359 what the value will be. For example, if the compiler can prove that
1360 the value of variable 'a' is always zero, it can optimize this code:
1363 do_something_with(tmp);
1369 This transformation is a win for single-threaded code because it gets
1370 rid of a load and a branch. The problem is that the compiler will
1371 carry out its proof assuming that the current CPU is the only one
1372 updating variable 'a'. If variable 'a' is shared, then the compiler's
1373 proof will be erroneous. Use ACCESS_ONCE() to tell the compiler
1374 that it doesn't know as much as it thinks it does:
1376 while (tmp = ACCESS_ONCE(a))
1377 do_something_with(tmp);
1379 But please note that the compiler is also closely watching what you
1380 do with the value after the ACCESS_ONCE(). For example, suppose you
1381 do the following and MAX is a preprocessor macro with the value 1:
1383 while ((tmp = ACCESS_ONCE(a)) % MAX)
1384 do_something_with(tmp);
1386 Then the compiler knows that the result of the "%" operator applied
1387 to MAX will always be zero, again allowing the compiler to optimize
1388 the code into near-nonexistence. (It will still load from the
1391 (*) Similarly, the compiler is within its rights to omit a store entirely
1392 if it knows that the variable already has the value being stored.
1393 Again, the compiler assumes that the current CPU is the only one
1394 storing into the variable, which can cause the compiler to do the
1395 wrong thing for shared variables. For example, suppose you have
1399 /* Code that does not store to variable a. */
1402 The compiler sees that the value of variable 'a' is already zero, so
1403 it might well omit the second store. This would come as a fatal
1404 surprise if some other CPU might have stored to variable 'a' in the
1407 Use ACCESS_ONCE() to prevent the compiler from making this sort of
1411 /* Code that does not store to variable a. */
1414 (*) The compiler is within its rights to reorder memory accesses unless
1415 you tell it not to. For example, consider the following interaction
1416 between process-level code and an interrupt handler:
1418 void process_level(void)
1420 msg = get_message();
1424 void interrupt_handler(void)
1427 process_message(msg);
1430 There is nothing to prevent the compiler from transforming
1431 process_level() to the following, in fact, this might well be a
1432 win for single-threaded code:
1434 void process_level(void)
1437 msg = get_message();
1440 If the interrupt occurs between these two statement, then
1441 interrupt_handler() might be passed a garbled msg. Use ACCESS_ONCE()
1442 to prevent this as follows:
1444 void process_level(void)
1446 ACCESS_ONCE(msg) = get_message();
1447 ACCESS_ONCE(flag) = true;
1450 void interrupt_handler(void)
1452 if (ACCESS_ONCE(flag))
1453 process_message(ACCESS_ONCE(msg));
1456 Note that the ACCESS_ONCE() wrappers in interrupt_handler()
1457 are needed if this interrupt handler can itself be interrupted
1458 by something that also accesses 'flag' and 'msg', for example,
1459 a nested interrupt or an NMI. Otherwise, ACCESS_ONCE() is not
1460 needed in interrupt_handler() other than for documentation purposes.
1461 (Note also that nested interrupts do not typically occur in modern
1462 Linux kernels, in fact, if an interrupt handler returns with
1463 interrupts enabled, you will get a WARN_ONCE() splat.)
1465 You should assume that the compiler can move ACCESS_ONCE() past
1466 code not containing ACCESS_ONCE(), barrier(), or similar primitives.
1468 This effect could also be achieved using barrier(), but ACCESS_ONCE()
1469 is more selective: With ACCESS_ONCE(), the compiler need only forget
1470 the contents of the indicated memory locations, while with barrier()
1471 the compiler must discard the value of all memory locations that
1472 it has currented cached in any machine registers. Of course,
1473 the compiler must also respect the order in which the ACCESS_ONCE()s
1474 occur, though the CPU of course need not do so.
1476 (*) The compiler is within its rights to invent stores to a variable,
1477 as in the following example:
1484 The compiler might save a branch by optimizing this as follows:
1490 In single-threaded code, this is not only safe, but also saves
1491 a branch. Unfortunately, in concurrent code, this optimization
1492 could cause some other CPU to see a spurious value of 42 -- even
1493 if variable 'a' was never zero -- when loading variable 'b'.
1494 Use ACCESS_ONCE() to prevent this as follows:
1499 ACCESS_ONCE(b) = 42;
1501 The compiler can also invent loads. These are usually less
1502 damaging, but they can result in cache-line bouncing and thus in
1503 poor performance and scalability. Use ACCESS_ONCE() to prevent
1506 (*) For aligned memory locations whose size allows them to be accessed
1507 with a single memory-reference instruction, prevents "load tearing"
1508 and "store tearing," in which a single large access is replaced by
1509 multiple smaller accesses. For example, given an architecture having
1510 16-bit store instructions with 7-bit immediate fields, the compiler
1511 might be tempted to use two 16-bit store-immediate instructions to
1512 implement the following 32-bit store:
1516 Please note that GCC really does use this sort of optimization,
1517 which is not surprising given that it would likely take more
1518 than two instructions to build the constant and then store it.
1519 This optimization can therefore be a win in single-threaded code.
1520 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1521 this optimization in a volatile store. In the absence of such bugs,
1522 use of ACCESS_ONCE() prevents store tearing in the following example:
1524 ACCESS_ONCE(p) = 0x00010002;
1526 Use of packed structures can also result in load and store tearing,
1529 struct __attribute__((__packed__)) foo {
1534 struct foo foo1, foo2;
1541 Because there are no ACCESS_ONCE() wrappers and no volatile markings,
1542 the compiler would be well within its rights to implement these three
1543 assignment statements as a pair of 32-bit loads followed by a pair
1544 of 32-bit stores. This would result in load tearing on 'foo1.b'
1545 and store tearing on 'foo2.b'. ACCESS_ONCE() again prevents tearing
1549 ACCESS_ONCE(foo2.b) = ACCESS_ONCE(foo1.b);
1552 All that aside, it is never necessary to use ACCESS_ONCE() on a variable
1553 that has been marked volatile. For example, because 'jiffies' is marked
1554 volatile, it is never necessary to say ACCESS_ONCE(jiffies). The reason
1555 for this is that ACCESS_ONCE() is implemented as a volatile cast, which
1556 has no effect when its argument is already marked volatile.
1558 Please note that these compiler barriers have no direct effect on the CPU,
1559 which may then reorder things however it wishes.
1565 The Linux kernel has eight basic CPU memory barriers:
1567 TYPE MANDATORY SMP CONDITIONAL
1568 =============== ======================= ===========================
1569 GENERAL mb() smp_mb()
1570 WRITE wmb() smp_wmb()
1571 READ rmb() smp_rmb()
1572 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1575 All memory barriers except the data dependency barriers imply a compiler
1576 barrier. Data dependencies do not impose any additional compiler ordering.
1578 Aside: In the case of data dependencies, the compiler would be expected to
1579 issue the loads in the correct order (eg. `a[b]` would have to load the value
1580 of b before loading a[b]), however there is no guarantee in the C specification
1581 that the compiler may not speculate the value of b (eg. is equal to 1) and load
1582 a before b (eg. tmp = a[1]; if (b != 1) tmp = a[b]; ). There is also the
1583 problem of a compiler reloading b after having loaded a[b], thus having a newer
1584 copy of b than a[b]. A consensus has not yet been reached about these problems,
1585 however the ACCESS_ONCE macro is a good place to start looking.
1587 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1588 systems because it is assumed that a CPU will appear to be self-consistent,
1589 and will order overlapping accesses correctly with respect to itself.
1591 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1592 references to shared memory on SMP systems, though the use of locking instead
1595 Mandatory barriers should not be used to control SMP effects, since mandatory
1596 barriers unnecessarily impose overhead on UP systems. They may, however, be
1597 used to control MMIO effects on accesses through relaxed memory I/O windows.
1598 These are required even on non-SMP systems as they affect the order in which
1599 memory operations appear to a device by prohibiting both the compiler and the
1600 CPU from reordering them.
1603 There are some more advanced barrier functions:
1605 (*) set_mb(var, value)
1607 This assigns the value to the variable and then inserts a full memory
1608 barrier after it, depending on the function. It isn't guaranteed to
1609 insert anything more than a compiler barrier in a UP compilation.
1612 (*) smp_mb__before_atomic();
1613 (*) smp_mb__after_atomic();
1615 These are for use with atomic (such as add, subtract, increment and
1616 decrement) functions that don't return a value, especially when used for
1617 reference counting. These functions do not imply memory barriers.
1619 These are also used for atomic bitop functions that do not return a
1620 value (such as set_bit and clear_bit).
1622 As an example, consider a piece of code that marks an object as being dead
1623 and then decrements the object's reference count:
1626 smp_mb__before_atomic();
1627 atomic_dec(&obj->ref_count);
1629 This makes sure that the death mark on the object is perceived to be set
1630 *before* the reference counter is decremented.
1632 See Documentation/atomic_ops.txt for more information. See the "Atomic
1633 operations" subsection for information on where to use these.
1639 The Linux kernel also has a special barrier for use with memory-mapped I/O
1644 This is a variation on the mandatory write barrier that causes writes to weakly
1645 ordered I/O regions to be partially ordered. Its effects may go beyond the
1646 CPU->Hardware interface and actually affect the hardware at some level.
1648 See the subsection "Locks vs I/O accesses" for more information.
1651 ===============================
1652 IMPLICIT KERNEL MEMORY BARRIERS
1653 ===============================
1655 Some of the other functions in the linux kernel imply memory barriers, amongst
1656 which are locking and scheduling functions.
1658 This specification is a _minimum_ guarantee; any particular architecture may
1659 provide more substantial guarantees, but these may not be relied upon outside
1660 of arch specific code.
1666 The Linux kernel has a number of locking constructs:
1675 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
1676 for each construct. These operations all imply certain barriers:
1678 (1) ACQUIRE operation implication:
1680 Memory operations issued after the ACQUIRE will be completed after the
1681 ACQUIRE operation has completed.
1683 Memory operations issued before the ACQUIRE may be completed after
1684 the ACQUIRE operation has completed. An smp_mb__before_spinlock(),
1685 combined with a following ACQUIRE, orders prior loads against
1686 subsequent loads and stores and also orders prior stores against
1687 subsequent stores. Note that this is weaker than smp_mb()! The
1688 smp_mb__before_spinlock() primitive is free on many architectures.
1690 (2) RELEASE operation implication:
1692 Memory operations issued before the RELEASE will be completed before the
1693 RELEASE operation has completed.
1695 Memory operations issued after the RELEASE may be completed before the
1696 RELEASE operation has completed.
1698 (3) ACQUIRE vs ACQUIRE implication:
1700 All ACQUIRE operations issued before another ACQUIRE operation will be
1701 completed before that ACQUIRE operation.
1703 (4) ACQUIRE vs RELEASE implication:
1705 All ACQUIRE operations issued before a RELEASE operation will be
1706 completed before the RELEASE operation.
1708 (5) Failed conditional ACQUIRE implication:
1710 Certain locking variants of the ACQUIRE operation may fail, either due to
1711 being unable to get the lock immediately, or due to receiving an unblocked
1712 signal whilst asleep waiting for the lock to become available. Failed
1713 locks do not imply any sort of barrier.
1715 [!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
1716 one-way barriers is that the effects of instructions outside of a critical
1717 section may seep into the inside of the critical section.
1719 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
1720 because it is possible for an access preceding the ACQUIRE to happen after the
1721 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
1722 the two accesses can themselves then cross:
1731 ACQUIRE M, STORE *B, STORE *A, RELEASE M
1733 When the ACQUIRE and RELEASE are a lock acquisition and release,
1734 respectively, this same reordering can occur if the lock's ACQUIRE and
1735 RELEASE are to the same lock variable, but only from the perspective of
1736 another CPU not holding that lock. In short, a ACQUIRE followed by an
1737 RELEASE may -not- be assumed to be a full memory barrier.
1739 Similarly, the reverse case of a RELEASE followed by an ACQUIRE does not
1740 imply a full memory barrier. If it is necessary for a RELEASE-ACQUIRE
1741 pair to produce a full barrier, the ACQUIRE can be followed by an
1742 smp_mb__after_unlock_lock() invocation. This will produce a full barrier
1743 if either (a) the RELEASE and the ACQUIRE are executed by the same
1744 CPU or task, or (b) the RELEASE and ACQUIRE act on the same variable.
1745 The smp_mb__after_unlock_lock() primitive is free on many architectures.
1746 Without smp_mb__after_unlock_lock(), the CPU's execution of the critical
1747 sections corresponding to the RELEASE and the ACQUIRE can cross, so that:
1756 ACQUIRE N, STORE *B, STORE *A, RELEASE M
1758 It might appear that this reordering could introduce a deadlock.
1759 However, this cannot happen because if such a deadlock threatened,
1760 the RELEASE would simply complete, thereby avoiding the deadlock.
1764 One key point is that we are only talking about the CPU doing
1765 the reordering, not the compiler. If the compiler (or, for
1766 that matter, the developer) switched the operations, deadlock
1769 But suppose the CPU reordered the operations. In this case,
1770 the unlock precedes the lock in the assembly code. The CPU
1771 simply elected to try executing the later lock operation first.
1772 If there is a deadlock, this lock operation will simply spin (or
1773 try to sleep, but more on that later). The CPU will eventually
1774 execute the unlock operation (which preceded the lock operation
1775 in the assembly code), which will unravel the potential deadlock,
1776 allowing the lock operation to succeed.
1778 But what if the lock is a sleeplock? In that case, the code will
1779 try to enter the scheduler, where it will eventually encounter
1780 a memory barrier, which will force the earlier unlock operation
1781 to complete, again unraveling the deadlock. There might be
1782 a sleep-unlock race, but the locking primitive needs to resolve
1783 such races properly in any case.
1785 With smp_mb__after_unlock_lock(), the two critical sections cannot overlap.
1786 For example, with the following code, the store to *A will always be
1787 seen by other CPUs before the store to *B:
1792 smp_mb__after_unlock_lock();
1795 The operations will always occur in one of the following orders:
1797 STORE *A, RELEASE, ACQUIRE, smp_mb__after_unlock_lock(), STORE *B
1798 STORE *A, ACQUIRE, RELEASE, smp_mb__after_unlock_lock(), STORE *B
1799 ACQUIRE, STORE *A, RELEASE, smp_mb__after_unlock_lock(), STORE *B
1801 If the RELEASE and ACQUIRE were instead both operating on the same lock
1802 variable, only the first of these alternatives can occur. In addition,
1803 the more strongly ordered systems may rule out some of the above orders.
1804 But in any case, as noted earlier, the smp_mb__after_unlock_lock()
1805 ensures that the store to *A will always be seen as happening before
1808 Locks and semaphores may not provide any guarantee of ordering on UP compiled
1809 systems, and so cannot be counted on in such a situation to actually achieve
1810 anything at all - especially with respect to I/O accesses - unless combined
1811 with interrupt disabling operations.
1813 See also the section on "Inter-CPU locking barrier effects".
1816 As an example, consider the following:
1827 The following sequence of events is acceptable:
1829 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
1831 [+] Note that {*F,*A} indicates a combined access.
1833 But none of the following are:
1835 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
1836 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
1837 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
1838 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
1842 INTERRUPT DISABLING FUNCTIONS
1843 -----------------------------
1845 Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
1846 (RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
1847 barriers are required in such a situation, they must be provided from some
1851 SLEEP AND WAKE-UP FUNCTIONS
1852 ---------------------------
1854 Sleeping and waking on an event flagged in global data can be viewed as an
1855 interaction between two pieces of data: the task state of the task waiting for
1856 the event and the global data used to indicate the event. To make sure that
1857 these appear to happen in the right order, the primitives to begin the process
1858 of going to sleep, and the primitives to initiate a wake up imply certain
1861 Firstly, the sleeper normally follows something like this sequence of events:
1864 set_current_state(TASK_UNINTERRUPTIBLE);
1865 if (event_indicated)
1870 A general memory barrier is interpolated automatically by set_current_state()
1871 after it has altered the task state:
1874 ===============================
1875 set_current_state();
1877 STORE current->state
1879 LOAD event_indicated
1881 set_current_state() may be wrapped by:
1884 prepare_to_wait_exclusive();
1886 which therefore also imply a general memory barrier after setting the state.
1887 The whole sequence above is available in various canned forms, all of which
1888 interpolate the memory barrier in the right place:
1891 wait_event_interruptible();
1892 wait_event_interruptible_exclusive();
1893 wait_event_interruptible_timeout();
1894 wait_event_killable();
1895 wait_event_timeout();
1900 Secondly, code that performs a wake up normally follows something like this:
1902 event_indicated = 1;
1903 wake_up(&event_wait_queue);
1907 event_indicated = 1;
1908 wake_up_process(event_daemon);
1910 A write memory barrier is implied by wake_up() and co. if and only if they wake
1911 something up. The barrier occurs before the task state is cleared, and so sits
1912 between the STORE to indicate the event and the STORE to set TASK_RUNNING:
1915 =============================== ===============================
1916 set_current_state(); STORE event_indicated
1917 set_mb(); wake_up();
1918 STORE current->state <write barrier>
1919 <general barrier> STORE current->state
1920 LOAD event_indicated
1922 To repeat, this write memory barrier is present if and only if something
1923 is actually awakened. To see this, consider the following sequence of
1924 events, where X and Y are both initially zero:
1927 =============================== ===============================
1928 X = 1; STORE event_indicated
1929 smp_mb(); wake_up();
1930 Y = 1; wait_event(wq, Y == 1);
1931 wake_up(); load from Y sees 1, no memory barrier
1932 load from X might see 0
1934 In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
1937 The available waker functions include:
1943 wake_up_interruptible();
1944 wake_up_interruptible_all();
1945 wake_up_interruptible_nr();
1946 wake_up_interruptible_poll();
1947 wake_up_interruptible_sync();
1948 wake_up_interruptible_sync_poll();
1950 wake_up_locked_poll();
1956 [!] Note that the memory barriers implied by the sleeper and the waker do _not_
1957 order multiple stores before the wake-up with respect to loads of those stored
1958 values after the sleeper has called set_current_state(). For instance, if the
1961 set_current_state(TASK_INTERRUPTIBLE);
1962 if (event_indicated)
1964 __set_current_state(TASK_RUNNING);
1965 do_something(my_data);
1970 event_indicated = 1;
1971 wake_up(&event_wait_queue);
1973 there's no guarantee that the change to event_indicated will be perceived by
1974 the sleeper as coming after the change to my_data. In such a circumstance, the
1975 code on both sides must interpolate its own memory barriers between the
1976 separate data accesses. Thus the above sleeper ought to do:
1978 set_current_state(TASK_INTERRUPTIBLE);
1979 if (event_indicated) {
1981 do_something(my_data);
1984 and the waker should do:
1988 event_indicated = 1;
1989 wake_up(&event_wait_queue);
1992 MISCELLANEOUS FUNCTIONS
1993 -----------------------
1995 Other functions that imply barriers:
1997 (*) schedule() and similar imply full memory barriers.
2000 ===================================
2001 INTER-CPU ACQUIRING BARRIER EFFECTS
2002 ===================================
2004 On SMP systems locking primitives give a more substantial form of barrier: one
2005 that does affect memory access ordering on other CPUs, within the context of
2006 conflict on any particular lock.
2009 ACQUIRES VS MEMORY ACCESSES
2010 ---------------------------
2012 Consider the following: the system has a pair of spinlocks (M) and (Q), and
2013 three CPUs; then should the following sequence of events occur:
2016 =============================== ===============================
2017 ACCESS_ONCE(*A) = a; ACCESS_ONCE(*E) = e;
2019 ACCESS_ONCE(*B) = b; ACCESS_ONCE(*F) = f;
2020 ACCESS_ONCE(*C) = c; ACCESS_ONCE(*G) = g;
2022 ACCESS_ONCE(*D) = d; ACCESS_ONCE(*H) = h;
2024 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2025 through *H occur in, other than the constraints imposed by the separate locks
2026 on the separate CPUs. It might, for example, see:
2028 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2030 But it won't see any of:
2032 *B, *C or *D preceding ACQUIRE M
2033 *A, *B or *C following RELEASE M
2034 *F, *G or *H preceding ACQUIRE Q
2035 *E, *F or *G following RELEASE Q
2038 However, if the following occurs:
2041 =============================== ===============================
2042 ACCESS_ONCE(*A) = a;
2044 ACCESS_ONCE(*B) = b;
2045 ACCESS_ONCE(*C) = c;
2047 ACCESS_ONCE(*D) = d; ACCESS_ONCE(*E) = e;
2049 smp_mb__after_unlock_lock();
2050 ACCESS_ONCE(*F) = f;
2051 ACCESS_ONCE(*G) = g;
2053 ACCESS_ONCE(*H) = h;
2057 *E, ACQUIRE M [1], *C, *B, *A, RELEASE M [1],
2058 ACQUIRE M [2], *H, *F, *G, RELEASE M [2], *D
2060 But assuming CPU 1 gets the lock first, CPU 3 won't see any of:
2062 *B, *C, *D, *F, *G or *H preceding ACQUIRE M [1]
2063 *A, *B or *C following RELEASE M [1]
2064 *F, *G or *H preceding ACQUIRE M [2]
2065 *A, *B, *C, *E, *F or *G following RELEASE M [2]
2067 Note that the smp_mb__after_unlock_lock() is critically important
2068 here: Without it CPU 3 might see some of the above orderings.
2069 Without smp_mb__after_unlock_lock(), the accesses are not guaranteed
2070 to be seen in order unless CPU 3 holds lock M.
2073 ACQUIRES VS I/O ACCESSES
2074 ------------------------
2076 Under certain circumstances (especially involving NUMA), I/O accesses within
2077 two spinlocked sections on two different CPUs may be seen as interleaved by the
2078 PCI bridge, because the PCI bridge does not necessarily participate in the
2079 cache-coherence protocol, and is therefore incapable of issuing the required
2080 read memory barriers.
2085 =============================== ===============================
2095 may be seen by the PCI bridge as follows:
2097 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
2099 which would probably cause the hardware to malfunction.
2102 What is necessary here is to intervene with an mmiowb() before dropping the
2103 spinlock, for example:
2106 =============================== ===============================
2118 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2119 before either of the stores issued on CPU 2.
2122 Furthermore, following a store by a load from the same device obviates the need
2123 for the mmiowb(), because the load forces the store to complete before the load
2127 =============================== ===============================
2138 See Documentation/DocBook/deviceiobook.tmpl for more information.
2141 =================================
2142 WHERE ARE MEMORY BARRIERS NEEDED?
2143 =================================
2145 Under normal operation, memory operation reordering is generally not going to
2146 be a problem as a single-threaded linear piece of code will still appear to
2147 work correctly, even if it's in an SMP kernel. There are, however, four
2148 circumstances in which reordering definitely _could_ be a problem:
2150 (*) Interprocessor interaction.
2152 (*) Atomic operations.
2154 (*) Accessing devices.
2159 INTERPROCESSOR INTERACTION
2160 --------------------------
2162 When there's a system with more than one processor, more than one CPU in the
2163 system may be working on the same data set at the same time. This can cause
2164 synchronisation problems, and the usual way of dealing with them is to use
2165 locks. Locks, however, are quite expensive, and so it may be preferable to
2166 operate without the use of a lock if at all possible. In such a case
2167 operations that affect both CPUs may have to be carefully ordered to prevent
2170 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2171 queued on the semaphore, by virtue of it having a piece of its stack linked to
2172 the semaphore's list of waiting processes:
2174 struct rw_semaphore {
2177 struct list_head waiters;
2180 struct rwsem_waiter {
2181 struct list_head list;
2182 struct task_struct *task;
2185 To wake up a particular waiter, the up_read() or up_write() functions have to:
2187 (1) read the next pointer from this waiter's record to know as to where the
2188 next waiter record is;
2190 (2) read the pointer to the waiter's task structure;
2192 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2194 (4) call wake_up_process() on the task; and
2196 (5) release the reference held on the waiter's task struct.
2198 In other words, it has to perform this sequence of events:
2200 LOAD waiter->list.next;
2206 and if any of these steps occur out of order, then the whole thing may
2209 Once it has queued itself and dropped the semaphore lock, the waiter does not
2210 get the lock again; it instead just waits for its task pointer to be cleared
2211 before proceeding. Since the record is on the waiter's stack, this means that
2212 if the task pointer is cleared _before_ the next pointer in the list is read,
2213 another CPU might start processing the waiter and might clobber the waiter's
2214 stack before the up*() function has a chance to read the next pointer.
2216 Consider then what might happen to the above sequence of events:
2219 =============================== ===============================
2226 Woken up by other event
2231 foo() clobbers *waiter
2233 LOAD waiter->list.next;
2236 This could be dealt with using the semaphore lock, but then the down_xxx()
2237 function has to needlessly get the spinlock again after being woken up.
2239 The way to deal with this is to insert a general SMP memory barrier:
2241 LOAD waiter->list.next;
2248 In this case, the barrier makes a guarantee that all memory accesses before the
2249 barrier will appear to happen before all the memory accesses after the barrier
2250 with respect to the other CPUs on the system. It does _not_ guarantee that all
2251 the memory accesses before the barrier will be complete by the time the barrier
2252 instruction itself is complete.
2254 On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2255 compiler barrier, thus making sure the compiler emits the instructions in the
2256 right order without actually intervening in the CPU. Since there's only one
2257 CPU, that CPU's dependency ordering logic will take care of everything else.
2263 Whilst they are technically interprocessor interaction considerations, atomic
2264 operations are noted specially as some of them imply full memory barriers and
2265 some don't, but they're very heavily relied on as a group throughout the
2268 Any atomic operation that modifies some state in memory and returns information
2269 about the state (old or new) implies an SMP-conditional general memory barrier
2270 (smp_mb()) on each side of the actual operation (with the exception of
2271 explicit lock operations, described later). These include:
2275 atomic_xchg(); atomic_long_xchg();
2276 atomic_cmpxchg(); atomic_long_cmpxchg();
2277 atomic_inc_return(); atomic_long_inc_return();
2278 atomic_dec_return(); atomic_long_dec_return();
2279 atomic_add_return(); atomic_long_add_return();
2280 atomic_sub_return(); atomic_long_sub_return();
2281 atomic_inc_and_test(); atomic_long_inc_and_test();
2282 atomic_dec_and_test(); atomic_long_dec_and_test();
2283 atomic_sub_and_test(); atomic_long_sub_and_test();
2284 atomic_add_negative(); atomic_long_add_negative();
2286 test_and_clear_bit();
2287 test_and_change_bit();
2289 /* when succeeds (returns 1) */
2290 atomic_add_unless(); atomic_long_add_unless();
2292 These are used for such things as implementing ACQUIRE-class and RELEASE-class
2293 operations and adjusting reference counters towards object destruction, and as
2294 such the implicit memory barrier effects are necessary.
2297 The following operations are potential problems as they do _not_ imply memory
2298 barriers, but might be used for implementing such things as RELEASE-class
2306 With these the appropriate explicit memory barrier should be used if necessary
2307 (smp_mb__before_atomic() for instance).
2310 The following also do _not_ imply memory barriers, and so may require explicit
2311 memory barriers under some circumstances (smp_mb__before_atomic() for
2319 If they're used for statistics generation, then they probably don't need memory
2320 barriers, unless there's a coupling between statistical data.
2322 If they're used for reference counting on an object to control its lifetime,
2323 they probably don't need memory barriers because either the reference count
2324 will be adjusted inside a locked section, or the caller will already hold
2325 sufficient references to make the lock, and thus a memory barrier unnecessary.
2327 If they're used for constructing a lock of some description, then they probably
2328 do need memory barriers as a lock primitive generally has to do things in a
2331 Basically, each usage case has to be carefully considered as to whether memory
2332 barriers are needed or not.
2334 The following operations are special locking primitives:
2336 test_and_set_bit_lock();
2338 __clear_bit_unlock();
2340 These implement ACQUIRE-class and RELEASE-class operations. These should be used in
2341 preference to other operations when implementing locking primitives, because
2342 their implementations can be optimised on many architectures.
2344 [!] Note that special memory barrier primitives are available for these
2345 situations because on some CPUs the atomic instructions used imply full memory
2346 barriers, and so barrier instructions are superfluous in conjunction with them,
2347 and in such cases the special barrier primitives will be no-ops.
2349 See Documentation/atomic_ops.txt for more information.
2355 Many devices can be memory mapped, and so appear to the CPU as if they're just
2356 a set of memory locations. To control such a device, the driver usually has to
2357 make the right memory accesses in exactly the right order.
2359 However, having a clever CPU or a clever compiler creates a potential problem
2360 in that the carefully sequenced accesses in the driver code won't reach the
2361 device in the requisite order if the CPU or the compiler thinks it is more
2362 efficient to reorder, combine or merge accesses - something that would cause
2363 the device to malfunction.
2365 Inside of the Linux kernel, I/O should be done through the appropriate accessor
2366 routines - such as inb() or writel() - which know how to make such accesses
2367 appropriately sequential. Whilst this, for the most part, renders the explicit
2368 use of memory barriers unnecessary, there are a couple of situations where they
2371 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
2372 so for _all_ general drivers locks should be used and mmiowb() must be
2373 issued prior to unlocking the critical section.
2375 (2) If the accessor functions are used to refer to an I/O memory window with
2376 relaxed memory access properties, then _mandatory_ memory barriers are
2377 required to enforce ordering.
2379 See Documentation/DocBook/deviceiobook.tmpl for more information.
2385 A driver may be interrupted by its own interrupt service routine, and thus the
2386 two parts of the driver may interfere with each other's attempts to control or
2389 This may be alleviated - at least in part - by disabling local interrupts (a
2390 form of locking), such that the critical operations are all contained within
2391 the interrupt-disabled section in the driver. Whilst the driver's interrupt
2392 routine is executing, the driver's core may not run on the same CPU, and its
2393 interrupt is not permitted to happen again until the current interrupt has been
2394 handled, thus the interrupt handler does not need to lock against that.
2396 However, consider a driver that was talking to an ethernet card that sports an
2397 address register and a data register. If that driver's core talks to the card
2398 under interrupt-disablement and then the driver's interrupt handler is invoked:
2409 The store to the data register might happen after the second store to the
2410 address register if ordering rules are sufficiently relaxed:
2412 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2415 If ordering rules are relaxed, it must be assumed that accesses done inside an
2416 interrupt disabled section may leak outside of it and may interleave with
2417 accesses performed in an interrupt - and vice versa - unless implicit or
2418 explicit barriers are used.
2420 Normally this won't be a problem because the I/O accesses done inside such
2421 sections will include synchronous load operations on strictly ordered I/O
2422 registers that form implicit I/O barriers. If this isn't sufficient then an
2423 mmiowb() may need to be used explicitly.
2426 A similar situation may occur between an interrupt routine and two routines
2427 running on separate CPUs that communicate with each other. If such a case is
2428 likely, then interrupt-disabling locks should be used to guarantee ordering.
2431 ==========================
2432 KERNEL I/O BARRIER EFFECTS
2433 ==========================
2435 When accessing I/O memory, drivers should use the appropriate accessor
2440 These are intended to talk to I/O space rather than memory space, but
2441 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
2442 indeed have special I/O space access cycles and instructions, but many
2443 CPUs don't have such a concept.
2445 The PCI bus, amongst others, defines an I/O space concept which - on such
2446 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
2447 space. However, it may also be mapped as a virtual I/O space in the CPU's
2448 memory map, particularly on those CPUs that don't support alternate I/O
2451 Accesses to this space may be fully synchronous (as on i386), but
2452 intermediary bridges (such as the PCI host bridge) may not fully honour
2455 They are guaranteed to be fully ordered with respect to each other.
2457 They are not guaranteed to be fully ordered with respect to other types of
2458 memory and I/O operation.
2460 (*) readX(), writeX():
2462 Whether these are guaranteed to be fully ordered and uncombined with
2463 respect to each other on the issuing CPU depends on the characteristics
2464 defined for the memory window through which they're accessing. On later
2465 i386 architecture machines, for example, this is controlled by way of the
2468 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
2469 provided they're not accessing a prefetchable device.
2471 However, intermediary hardware (such as a PCI bridge) may indulge in
2472 deferral if it so wishes; to flush a store, a load from the same location
2473 is preferred[*], but a load from the same device or from configuration
2474 space should suffice for PCI.
2476 [*] NOTE! attempting to load from the same location as was written to may
2477 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2480 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2481 force stores to be ordered.
2483 Please refer to the PCI specification for more information on interactions
2484 between PCI transactions.
2486 (*) readX_relaxed(), writeX_relaxed()
2488 These are similar to readX() and writeX(), but provide weaker memory
2489 ordering guarantees. Specifically, they do not guarantee ordering with
2490 respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
2491 ordering with respect to LOCK or UNLOCK operations. If the latter is
2492 required, an mmiowb() barrier can be used. Note that relaxed accesses to
2493 the same peripheral are guaranteed to be ordered with respect to each
2496 (*) ioreadX(), iowriteX()
2498 These will perform appropriately for the type of access they're actually
2499 doing, be it inX()/outX() or readX()/writeX().
2502 ========================================
2503 ASSUMED MINIMUM EXECUTION ORDERING MODEL
2504 ========================================
2506 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2507 maintain the appearance of program causality with respect to itself. Some CPUs
2508 (such as i386 or x86_64) are more constrained than others (such as powerpc or
2509 frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2510 of arch-specific code.
2512 This means that it must be considered that the CPU will execute its instruction
2513 stream in any order it feels like - or even in parallel - provided that if an
2514 instruction in the stream depends on an earlier instruction, then that
2515 earlier instruction must be sufficiently complete[*] before the later
2516 instruction may proceed; in other words: provided that the appearance of
2517 causality is maintained.
2519 [*] Some instructions have more than one effect - such as changing the
2520 condition codes, changing registers or changing memory - and different
2521 instructions may depend on different effects.
2523 A CPU may also discard any instruction sequence that winds up having no
2524 ultimate effect. For example, if two adjacent instructions both load an
2525 immediate value into the same register, the first may be discarded.
2528 Similarly, it has to be assumed that compiler might reorder the instruction
2529 stream in any way it sees fit, again provided the appearance of causality is
2533 ============================
2534 THE EFFECTS OF THE CPU CACHE
2535 ============================
2537 The way cached memory operations are perceived across the system is affected to
2538 a certain extent by the caches that lie between CPUs and memory, and by the
2539 memory coherence system that maintains the consistency of state in the system.
2541 As far as the way a CPU interacts with another part of the system through the
2542 caches goes, the memory system has to include the CPU's caches, and memory
2543 barriers for the most part act at the interface between the CPU and its cache
2544 (memory barriers logically act on the dotted line in the following diagram):
2546 <--- CPU ---> : <----------- Memory ----------->
2548 +--------+ +--------+ : +--------+ +-----------+
2549 | | | | : | | | | +--------+
2550 | CPU | | Memory | : | CPU | | | | |
2551 | Core |--->| Access |----->| Cache |<-->| | | |
2552 | | | Queue | : | | | |--->| Memory |
2553 | | | | : | | | | | |
2554 +--------+ +--------+ : +--------+ | | | |
2555 : | Cache | +--------+
2557 : | Mechanism | +--------+
2558 +--------+ +--------+ : +--------+ | | | |
2559 | | | | : | | | | | |
2560 | CPU | | Memory | : | CPU | | |--->| Device |
2561 | Core |--->| Access |----->| Cache |<-->| | | |
2562 | | | Queue | : | | | | | |
2563 | | | | : | | | | +--------+
2564 +--------+ +--------+ : +--------+ +-----------+
2568 Although any particular load or store may not actually appear outside of the
2569 CPU that issued it since it may have been satisfied within the CPU's own cache,
2570 it will still appear as if the full memory access had taken place as far as the
2571 other CPUs are concerned since the cache coherency mechanisms will migrate the
2572 cacheline over to the accessing CPU and propagate the effects upon conflict.
2574 The CPU core may execute instructions in any order it deems fit, provided the
2575 expected program causality appears to be maintained. Some of the instructions
2576 generate load and store operations which then go into the queue of memory
2577 accesses to be performed. The core may place these in the queue in any order
2578 it wishes, and continue execution until it is forced to wait for an instruction
2581 What memory barriers are concerned with is controlling the order in which
2582 accesses cross from the CPU side of things to the memory side of things, and
2583 the order in which the effects are perceived to happen by the other observers
2586 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2587 their own loads and stores as if they had happened in program order.
2589 [!] MMIO or other device accesses may bypass the cache system. This depends on
2590 the properties of the memory window through which devices are accessed and/or
2591 the use of any special device communication instructions the CPU may have.
2597 Life isn't quite as simple as it may appear above, however: for while the
2598 caches are expected to be coherent, there's no guarantee that that coherency
2599 will be ordered. This means that whilst changes made on one CPU will
2600 eventually become visible on all CPUs, there's no guarantee that they will
2601 become apparent in the same order on those other CPUs.
2604 Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2605 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2610 +--------+ : +--->| Cache A |<------->| |
2611 | | : | +---------+ | |
2613 | | : | +---------+ | |
2614 +--------+ : +--->| Cache B |<------->| |
2617 : +---------+ | System |
2618 +--------+ : +--->| Cache C |<------->| |
2619 | | : | +---------+ | |
2621 | | : | +---------+ | |
2622 +--------+ : +--->| Cache D |<------->| |
2627 Imagine the system has the following properties:
2629 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2632 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2635 (*) whilst the CPU core is interrogating one cache, the other cache may be
2636 making use of the bus to access the rest of the system - perhaps to
2637 displace a dirty cacheline or to do a speculative load;
2639 (*) each cache has a queue of operations that need to be applied to that cache
2640 to maintain coherency with the rest of the system;
2642 (*) the coherency queue is not flushed by normal loads to lines already
2643 present in the cache, even though the contents of the queue may
2644 potentially affect those loads.
2646 Imagine, then, that two writes are made on the first CPU, with a write barrier
2647 between them to guarantee that they will appear to reach that CPU's caches in
2648 the requisite order:
2651 =============== =============== =======================================
2652 u == 0, v == 1 and p == &u, q == &u
2654 smp_wmb(); Make sure change to v is visible before
2656 <A:modify v=2> v is now in cache A exclusively
2658 <B:modify p=&v> p is now in cache B exclusively
2660 The write memory barrier forces the other CPUs in the system to perceive that
2661 the local CPU's caches have apparently been updated in the correct order. But
2662 now imagine that the second CPU wants to read those values:
2665 =============== =============== =======================================
2670 The above pair of reads may then fail to happen in the expected order, as the
2671 cacheline holding p may get updated in one of the second CPU's caches whilst
2672 the update to the cacheline holding v is delayed in the other of the second
2673 CPU's caches by some other cache event:
2676 =============== =============== =======================================
2677 u == 0, v == 1 and p == &u, q == &u
2680 <A:modify v=2> <C:busy>
2684 <B:modify p=&v> <D:commit p=&v>
2687 <C:read *q> Reads from v before v updated in cache
2691 Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2692 no guarantee that, without intervention, the order of update will be the same
2693 as that committed on CPU 1.
2696 To intervene, we need to interpolate a data dependency barrier or a read
2697 barrier between the loads. This will force the cache to commit its coherency
2698 queue before processing any further requests:
2701 =============== =============== =======================================
2702 u == 0, v == 1 and p == &u, q == &u
2705 <A:modify v=2> <C:busy>
2709 <B:modify p=&v> <D:commit p=&v>
2711 smp_read_barrier_depends()
2715 <C:read *q> Reads from v after v updated in cache
2718 This sort of problem can be encountered on DEC Alpha processors as they have a
2719 split cache that improves performance by making better use of the data bus.
2720 Whilst most CPUs do imply a data dependency barrier on the read when a memory
2721 access depends on a read, not all do, so it may not be relied on.
2723 Other CPUs may also have split caches, but must coordinate between the various
2724 cachelets for normal memory accesses. The semantics of the Alpha removes the
2725 need for coordination in the absence of memory barriers.
2728 CACHE COHERENCY VS DMA
2729 ----------------------
2731 Not all systems maintain cache coherency with respect to devices doing DMA. In
2732 such cases, a device attempting DMA may obtain stale data from RAM because
2733 dirty cache lines may be resident in the caches of various CPUs, and may not
2734 have been written back to RAM yet. To deal with this, the appropriate part of
2735 the kernel must flush the overlapping bits of cache on each CPU (and maybe
2736 invalidate them as well).
2738 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2739 cache lines being written back to RAM from a CPU's cache after the device has
2740 installed its own data, or cache lines present in the CPU's cache may simply
2741 obscure the fact that RAM has been updated, until at such time as the cacheline
2742 is discarded from the CPU's cache and reloaded. To deal with this, the
2743 appropriate part of the kernel must invalidate the overlapping bits of the
2746 See Documentation/cachetlb.txt for more information on cache management.
2749 CACHE COHERENCY VS MMIO
2750 -----------------------
2752 Memory mapped I/O usually takes place through memory locations that are part of
2753 a window in the CPU's memory space that has different properties assigned than
2754 the usual RAM directed window.
2756 Amongst these properties is usually the fact that such accesses bypass the
2757 caching entirely and go directly to the device buses. This means MMIO accesses
2758 may, in effect, overtake accesses to cached memory that were emitted earlier.
2759 A memory barrier isn't sufficient in such a case, but rather the cache must be
2760 flushed between the cached memory write and the MMIO access if the two are in
2764 =========================
2765 THE THINGS CPUS GET UP TO
2766 =========================
2768 A programmer might take it for granted that the CPU will perform memory
2769 operations in exactly the order specified, so that if the CPU is, for example,
2770 given the following piece of code to execute:
2772 a = ACCESS_ONCE(*A);
2773 ACCESS_ONCE(*B) = b;
2774 c = ACCESS_ONCE(*C);
2775 d = ACCESS_ONCE(*D);
2776 ACCESS_ONCE(*E) = e;
2778 they would then expect that the CPU will complete the memory operation for each
2779 instruction before moving on to the next one, leading to a definite sequence of
2780 operations as seen by external observers in the system:
2782 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2785 Reality is, of course, much messier. With many CPUs and compilers, the above
2786 assumption doesn't hold because:
2788 (*) loads are more likely to need to be completed immediately to permit
2789 execution progress, whereas stores can often be deferred without a
2792 (*) loads may be done speculatively, and the result discarded should it prove
2793 to have been unnecessary;
2795 (*) loads may be done speculatively, leading to the result having been fetched
2796 at the wrong time in the expected sequence of events;
2798 (*) the order of the memory accesses may be rearranged to promote better use
2799 of the CPU buses and caches;
2801 (*) loads and stores may be combined to improve performance when talking to
2802 memory or I/O hardware that can do batched accesses of adjacent locations,
2803 thus cutting down on transaction setup costs (memory and PCI devices may
2804 both be able to do this); and
2806 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2807 mechanisms may alleviate this - once the store has actually hit the cache
2808 - there's no guarantee that the coherency management will be propagated in
2809 order to other CPUs.
2811 So what another CPU, say, might actually observe from the above piece of code
2814 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2816 (Where "LOAD {*C,*D}" is a combined load)
2819 However, it is guaranteed that a CPU will be self-consistent: it will see its
2820 _own_ accesses appear to be correctly ordered, without the need for a memory
2821 barrier. For instance with the following code:
2823 U = ACCESS_ONCE(*A);
2824 ACCESS_ONCE(*A) = V;
2825 ACCESS_ONCE(*A) = W;
2826 X = ACCESS_ONCE(*A);
2827 ACCESS_ONCE(*A) = Y;
2828 Z = ACCESS_ONCE(*A);
2830 and assuming no intervention by an external influence, it can be assumed that
2831 the final result will appear to be:
2833 U == the original value of *A
2838 The code above may cause the CPU to generate the full sequence of memory
2841 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2843 in that order, but, without intervention, the sequence may have almost any
2844 combination of elements combined or discarded, provided the program's view of
2845 the world remains consistent. Note that ACCESS_ONCE() is -not- optional
2846 in the above example, as there are architectures where a given CPU might
2847 reorder successive loads to the same location. On such architectures,
2848 ACCESS_ONCE() does whatever is necessary to prevent this, for example, on
2849 Itanium the volatile casts used by ACCESS_ONCE() cause GCC to emit the
2850 special ld.acq and st.rel instructions that prevent such reordering.
2852 The compiler may also combine, discard or defer elements of the sequence before
2853 the CPU even sees them.
2864 since, without either a write barrier or an ACCESS_ONCE(), it can be
2865 assumed that the effect of the storage of V to *A is lost. Similarly:
2870 may, without a memory barrier or an ACCESS_ONCE(), be reduced to:
2875 and the LOAD operation never appear outside of the CPU.
2878 AND THEN THERE'S THE ALPHA
2879 --------------------------
2881 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2882 some versions of the Alpha CPU have a split data cache, permitting them to have
2883 two semantically-related cache lines updated at separate times. This is where
2884 the data dependency barrier really becomes necessary as this synchronises both
2885 caches with the memory coherence system, thus making it seem like pointer
2886 changes vs new data occur in the right order.
2888 The Alpha defines the Linux kernel's memory barrier model.
2890 See the subsection on "Cache Coherency" above.
2900 Memory barriers can be used to implement circular buffering without the need
2901 of a lock to serialise the producer with the consumer. See:
2903 Documentation/circular-buffers.txt
2912 Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2914 Chapter 5.2: Physical Address Space Characteristics
2915 Chapter 5.4: Caches and Write Buffers
2916 Chapter 5.5: Data Sharing
2917 Chapter 5.6: Read/Write Ordering
2919 AMD64 Architecture Programmer's Manual Volume 2: System Programming
2920 Chapter 7.1: Memory-Access Ordering
2921 Chapter 7.4: Buffering and Combining Memory Writes
2923 IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2924 System Programming Guide
2925 Chapter 7.1: Locked Atomic Operations
2926 Chapter 7.2: Memory Ordering
2927 Chapter 7.4: Serializing Instructions
2929 The SPARC Architecture Manual, Version 9
2930 Chapter 8: Memory Models
2931 Appendix D: Formal Specification of the Memory Models
2932 Appendix J: Programming with the Memory Models
2934 UltraSPARC Programmer Reference Manual
2935 Chapter 5: Memory Accesses and Cacheability
2936 Chapter 15: Sparc-V9 Memory Models
2938 UltraSPARC III Cu User's Manual
2939 Chapter 9: Memory Models
2941 UltraSPARC IIIi Processor User's Manual
2942 Chapter 8: Memory Models
2944 UltraSPARC Architecture 2005
2946 Appendix D: Formal Specifications of the Memory Models
2948 UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
2949 Chapter 8: Memory Models
2950 Appendix F: Caches and Cache Coherency
2952 Solaris Internals, Core Kernel Architecture, p63-68:
2953 Chapter 3.3: Hardware Considerations for Locks and
2956 Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
2957 for Kernel Programmers:
2958 Chapter 13: Other Memory Models
2960 Intel Itanium Architecture Software Developer's Manual: Volume 1:
2961 Section 2.6: Speculation
2962 Section 4.4: Memory Access
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