Documentation/xtensa/mmu.txt

   1 MMUv3 initialization sequence.
   2
   3 The code in the initialize_mmu macro sets up MMUv3 memory mapping
   4 identically to MMUv2 fixed memory mapping. Depending on
   5 CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is
   6 located in one of the following address ranges:
   7
   8     0xF0000000..0xFFFFFFFF (will keep same address in MMU v2 layout;
   9                          typically ROM)
  10     0x00000000..0x07FFFFFF (system RAM; this code is actually linked
  11                          at 0xD0000000..0xD7FFFFFF [cached]
  12                          or 0xD8000000..0xDFFFFFFF [uncached];
  13                          in any case, initially runs elsewhere
  14                          than linked, so have to be careful)
  15
  16 The code has the following assumptions:
  17   This code fragment is run only on an MMU v3.
  18   TLBs are in their reset state.
  19   ITLBCFG and DTLBCFG are zero (reset state).
  20   RASID is 0x04030201 (reset state).
  21   PS.RING is zero (reset state).
  22   LITBASE is zero (reset state, PC-relative literals); required to be PIC.
  23
  24 TLB setup proceeds along the following steps.
  25
  26   Legend:
  27     VA = virtual address (two upper nibbles of it);
  28     PA = physical address (two upper nibbles of it);
  29     pc = physical range that contains this code;
  30
  31 After step 2, we jump to virtual address in 0x40000000..0x5fffffff
  32 that corresponds to next instruction to execute in this code.
  33 After step 4, we jump to intended (linked) address of this code.
  34
  35     Step 0     Step1     Step 2     Step3     Step 4     Step5
  36  ============  =====  ============  =====  ============  =====
  37    VA      PA     PA    VA      PA     PA    VA      PA     PA
  38  ------    --     --  ------    --     --  ------    --     --
  39  E0..FF -> E0  -> E0  E0..FF -> E0         F0..FF -> F0  -> F0
  40  C0..DF -> C0  -> C0  C0..DF -> C0         E0..EF -> F0  -> F0
  41  A0..BF -> A0  -> A0  A0..BF -> A0         D8..DF -> 00  -> 00
  42  80..9F -> 80  -> 80  80..9F -> 80         D0..D7 -> 00  -> 00
  43  60..7F -> 60  -> 60  60..7F -> 60
  44  40..5F -> 40         40..5F -> pc  -> pc  40..5F -> pc
  45  20..3F -> 20  -> 20  20..3F -> 20
  46  00..1F -> 00  -> 00  00..1F -> 00
  47
  48 The default location of IO peripherals is above 0xf0000000. This may change
  49 using a "ranges" property in a device tree simple-bus node. See ePAPR 1.1, §6.5
  50 for details on the syntax and semantic of simple-bus nodes. The following
  51 limitations apply:
  52
  53 1. Only top level simple-bus nodes are considered
  54
  55 2. Only one (first) simple-bus node is considered
  56
  57 3. Empty "ranges" properties are not supported
  58
  59 4. Only the first triplet in the "ranges" property is considered
  60
  61 5. The parent-bus-address value is rounded down to the nearest 256MB boundary
  62
  63 6. The IO area covers the entire 256MB segment of parent-bus-address; the
  64    "ranges" triplet length field is ignored
  65
  66
  67 MMUv3 address space layouts.
  68 ============================
  69
  70 Default MMUv2-compatible layout.
  71
  72                       Symbol                   VADDR       Size
  73 +------------------+
  74 | Userspace        |                           0x00000000  TASK_SIZE
  75 +------------------+                           0x40000000
  76 +------------------+
  77 | Page table       |                           0x80000000
  78 +------------------+                           0x80400000
  79 +------------------+
  80 | KMAP area        |  PKMAP_BASE                           PTRS_PER_PTE *
  81 |                  |                                       DCACHE_N_COLORS *
  82 |                  |                                       PAGE_SIZE
  83 |                  |                                       (4MB * DCACHE_N_COLORS)
  84 +------------------+
  85 | Atomic KMAP area |  FIXADDR_START                        KM_TYPE_NR *
  86 |                  |                                       NR_CPUS *
  87 |                  |                                       DCACHE_N_COLORS *
  88 |                  |                                       PAGE_SIZE
  89 +------------------+  FIXADDR_TOP              0xbffff000
  90 +------------------+
  91 | VMALLOC area     |  VMALLOC_START            0xc0000000  128MB - 64KB
  92 +------------------+  VMALLOC_END
  93 | Cache aliasing   |  TLBTEMP_BASE_1           0xc7ff0000  DCACHE_WAY_SIZE
  94 | remap area 1     |
  95 +------------------+
  96 | Cache aliasing   |  TLBTEMP_BASE_2                       DCACHE_WAY_SIZE
  97 | remap area 2     |
  98 +------------------+
  99 +------------------+
 100 | Cached KSEG      |  XCHAL_KSEG_CACHED_VADDR  0xd0000000  128MB
 101 +------------------+
 102 | Uncached KSEG    |  XCHAL_KSEG_BYPASS_VADDR  0xd8000000  128MB
 103 +------------------+
 104 | Cached KIO       |  XCHAL_KIO_CACHED_VADDR   0xe0000000  256MB
 105 +------------------+
 106 | Uncached KIO     |  XCHAL_KIO_BYPASS_VADDR   0xf0000000  256MB
 107 +------------------+
 108
 109
 110 256MB cached + 256MB uncached layout.
 111
 112                       Symbol                   VADDR       Size
 113 +------------------+
 114 | Userspace        |                           0x00000000  TASK_SIZE
 115 +------------------+                           0x40000000
 116 +------------------+
 117 | Page table       |                           0x80000000
 118 +------------------+                           0x80400000
 119 +------------------+
 120 | KMAP area        |  PKMAP_BASE                           PTRS_PER_PTE *
 121 |                  |                                       DCACHE_N_COLORS *
 122 |                  |                                       PAGE_SIZE
 123 |                  |                                       (4MB * DCACHE_N_COLORS)
 124 +------------------+
 125 | Atomic KMAP area |  FIXADDR_START                        KM_TYPE_NR *
 126 |                  |                                       NR_CPUS *
 127 |                  |                                       DCACHE_N_COLORS *
 128 |                  |                                       PAGE_SIZE
 129 +------------------+  FIXADDR_TOP              0x9ffff000
 130 +------------------+
 131 | VMALLOC area     |  VMALLOC_START            0xa0000000  128MB - 64KB
 132 +------------------+  VMALLOC_END
 133 | Cache aliasing   |  TLBTEMP_BASE_1           0xa7ff0000  DCACHE_WAY_SIZE
 134 | remap area 1     |
 135 +------------------+
 136 | Cache aliasing   |  TLBTEMP_BASE_2                       DCACHE_WAY_SIZE
 137 | remap area 2     |
 138 +------------------+
 139 +------------------+
 140 | Cached KSEG      |  XCHAL_KSEG_CACHED_VADDR  0xb0000000  256MB
 141 +------------------+
 142 | Uncached KSEG    |  XCHAL_KSEG_BYPASS_VADDR  0xc0000000  256MB
 143 +------------------+
 144 +------------------+
 145 | Cached KIO       |  XCHAL_KIO_CACHED_VADDR   0xe0000000  256MB
 146 +------------------+
 147 | Uncached KIO     |  XCHAL_KIO_BYPASS_VADDR   0xf0000000  256MB
 148 +------------------+
 149
 150
 151 512MB cached + 512MB uncached layout.
 152
 153                       Symbol                   VADDR       Size
 154 +------------------+
 155 | Userspace        |                           0x00000000  TASK_SIZE
 156 +------------------+                           0x40000000
 157 +------------------+
 158 | Page table       |                           0x80000000
 159 +------------------+                           0x80400000
 160 +------------------+
 161 | KMAP area        |  PKMAP_BASE                           PTRS_PER_PTE *
 162 |                  |                                       DCACHE_N_COLORS *
 163 |                  |                                       PAGE_SIZE
 164 |                  |                                       (4MB * DCACHE_N_COLORS)
 165 +------------------+
 166 | Atomic KMAP area |  FIXADDR_START                        KM_TYPE_NR *
 167 |                  |                                       NR_CPUS *
 168 |                  |                                       DCACHE_N_COLORS *
 169 |                  |                                       PAGE_SIZE
 170 +------------------+  FIXADDR_TOP              0x8ffff000
 171 +------------------+
 172 | VMALLOC area     |  VMALLOC_START            0x90000000  128MB - 64KB
 173 +------------------+  VMALLOC_END
 174 | Cache aliasing   |  TLBTEMP_BASE_1           0x97ff0000  DCACHE_WAY_SIZE
 175 | remap area 1     |
 176 +------------------+
 177 | Cache aliasing   |  TLBTEMP_BASE_2                       DCACHE_WAY_SIZE
 178 | remap area 2     |
 179 +------------------+
 180 +------------------+
 181 | Cached KSEG      |  XCHAL_KSEG_CACHED_VADDR  0xa0000000  512MB
 182 +------------------+
 183 | Uncached KSEG    |  XCHAL_KSEG_BYPASS_VADDR  0xc0000000  512MB
 184 +------------------+
 185 | Cached KIO       |  XCHAL_KIO_CACHED_VADDR   0xe0000000  256MB
 186 +------------------+
 187 | Uncached KIO     |  XCHAL_KIO_BYPASS_VADDR   0xf0000000  256MB
 188 +------------------+