2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
11 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
12 select BUILDTIME_EXTABLE_SORT
14 select CLONE_BACKWARDS
15 # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
16 select DEVTMPFS if !INITRAMFS_SOURCE=""
17 select GENERIC_ATOMIC64
18 select GENERIC_CLOCKEVENTS
19 select GENERIC_FIND_FIRST_BIT
20 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_PENDING_IRQ if SMP
24 select GENERIC_SMP_IDLE_THREAD
26 select HAVE_ARCH_TRACEHOOK
27 select HAVE_FUTEX_CMPXCHG
28 select HAVE_IOREMAP_PROT
30 select HAVE_KRETPROBES
32 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
34 select HAVE_PERF_EVENTS
36 select MODULES_USE_ELF_RELA
39 select OF_EARLY_FLATTREE
40 select PERF_USE_VMALLOC
41 select HAVE_DEBUG_STACKOVERFLOW
46 config TRACE_IRQFLAGS_SUPPORT
49 config LOCKDEP_SUPPORT
52 config SCHED_OMIT_FRAME_POINTER
58 config RWSEM_GENERIC_SPINLOCK
61 config ARCH_FLATMEM_ENABLE
70 config GENERIC_CALIBRATE_DELAY
73 config GENERIC_HWEIGHT
76 config STACKTRACE_SUPPORT
80 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
85 source "kernel/Kconfig.freezer"
87 menu "ARC Architecture Configuration"
89 menu "ARC Platform/SoC/Board"
91 source "arch/arc/plat-sim/Kconfig"
92 source "arch/arc/plat-tb10x/Kconfig"
93 source "arch/arc/plat-axs10x/Kconfig"
94 #New platform adds here
99 prompt "ARC Instruction Set"
100 default ISA_ARCOMPACT
105 The original ARC ISA of ARC600/700 cores
110 ISA for the Next Generation ARC-HS cores
114 menu "ARC CPU Configuration"
118 default ARC_CPU_770 if ISA_ARCOMPACT
119 default ARC_CPU_HS if ISA_ARCV2
127 Support for ARC750 core
133 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
134 This core has a bunch of cool new features:
135 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
136 Shared Address Spaces (for sharing TLB entires in MMU)
137 -Caches: New Prog Model, Region Flush
138 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
146 Support for ARC HS38x Cores based on ARCv2 ISA
147 The notable features are:
148 - SMP configurations of upto 4 core with coherency
149 - Optional L2 Cache and IO-Coherency
150 - Revised Interrupt Architecture (multiple priorites, reg banks,
151 auto stack switch, auto regfile save/restore)
152 - MMUv4 (PIPT dcache, Huge Pages)
154 * 64bit load/store: LDD, STD
155 * Hardware assisted divide/remainder: DIV, REM
156 * Function prologue/epilogue: ENTER_S, LEAVE_S
157 * IRQ enable/disable: CLRI, SETI
158 * pop count: FFS, FLS
159 * SETcc, BMSKN, XBFU...
163 config CPU_BIG_ENDIAN
164 bool "Enable Big Endian Mode"
167 Build kernel for Big Endian Mode of ARC CPU
170 bool "Symmetric Multi-Processing"
172 select ARC_HAS_COH_CACHES if ISA_ARCV2
173 select ARC_MCIP if ISA_ARCV2
175 This enables support for systems with more than one CPU.
179 config ARC_HAS_COH_CACHES
182 config ARC_HAS_REENTRANT_IRQ_LV2
186 bool "ARConnect Multicore IP (MCIP) Support "
189 This IP block enables SMP in ARC-HS38 cores.
190 It provides for cross-core interrupts, multi-core debug
191 hardware semaphores, shared memory,....
194 int "Maximum number of CPUs (2-4096)"
198 config ARC_SMP_HALT_ON_RESET
199 bool "Enable Halt-on-reset boot mode"
200 default y if ARC_UBOOT_SUPPORT
202 In SMP configuration cores can be configured as Halt-on-reset
203 or they could all start at same time. For Halt-on-reset, non
204 masters are parked until Master kicks them so they can start of
205 at designated entry point. For other case, all jump to common
206 entry point and spin wait for Master's signal.
211 bool "Enable Cache Support"
213 # if SMP, cache enabled ONLY if ARC implementation has cache coherency
214 depends on !SMP || ARC_HAS_COH_CACHES
218 config ARC_CACHE_LINE_SHIFT
219 int "Cache Line Length (as power of 2)"
223 Starting with ARC700 4.9, Cache line length is configurable,
224 This option specifies "N", with Line-len = 2 power N
225 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
226 Linux only supports same line lengths for I and D caches.
228 config ARC_HAS_ICACHE
229 bool "Use Instruction Cache"
232 config ARC_HAS_DCACHE
233 bool "Use Data Cache"
236 config ARC_CACHE_PAGES
237 bool "Per Page Cache Control"
239 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
241 This can be used to over-ride the global I/D Cache Enable on a
242 per-page basis (but only for pages accessed via MMU such as
243 Kernel Virtual address or User Virtual Address)
244 TLB entries have a per-page Cache Enable Bit.
245 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
246 Global DISABLE + Per Page ENABLE won't work
248 config ARC_CACHE_VIPT_ALIASING
249 bool "Support VIPT Aliasing D$"
250 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
258 Single Cycle RAMS to store Fast Path Code
262 int "ICCM Size in KB"
264 depends on ARC_HAS_ICCM
269 Single Cycle RAMS to store Fast Path Data
273 int "DCCM Size in KB"
275 depends on ARC_HAS_DCCM
278 hex "DCCM map address"
280 depends on ARC_HAS_DCCM
282 config ARC_HAS_HW_MPY
283 bool "Use Hardware Multiplier (Normal or Faster XMAC)"
286 Influences how gcc generates code for MPY operations.
287 If enabled, MPYxx insns are generated, provided by Standard/XMAC
288 Multipler. Otherwise software multipy lib is used
292 default ARC_MMU_V3 if ARC_CPU_770
293 default ARC_MMU_V2 if ARC_CPU_750D
294 default ARC_MMU_V4 if ARC_CPU_HS
306 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
307 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
311 depends on ARC_CPU_770
313 Introduced with ARC700 4.10: New Features
314 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
315 Shared Address Spaces (SASID)
327 prompt "MMU Page Size"
328 default ARC_PAGE_SIZE_8K
330 config ARC_PAGE_SIZE_8K
333 Choose between 8k vs 16k
335 config ARC_PAGE_SIZE_16K
337 depends on ARC_MMU_V3 || ARC_MMU_V4
339 config ARC_PAGE_SIZE_4K
341 depends on ARC_MMU_V3 || ARC_MMU_V4
347 config ARC_COMPACT_IRQ_LEVELS
348 bool "ARCompact IRQ Priorities: High(2)/Low(1)"
350 # Timer HAS to be high priority, for any other high priority config
352 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
353 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
355 if ARC_COMPACT_IRQ_LEVELS
366 endif #ARC_COMPACT_IRQ_LEVELS
368 config ARC_FPU_SAVE_RESTORE
369 bool "Enable FPU state persistence across context switch"
372 Double Precision Floating Point unit had dedictaed regs which
373 need to be saved/restored across context-switch.
374 Note that ARC FPU is overly simplistic, unlike say x86, which has
375 hardware pieces to allow software to conditionally save/restore,
376 based on actual usage of FPU by a task. Thus our implemn does
377 this for all tasks in system.
385 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
387 depends on !ARC_CANT_LLSC
389 config ARC_STAR_9000923308
390 bool "Workaround for llock/scond livelock"
392 depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
395 bool "Insn: SWAPE (endian-swap)"
401 bool "Insn: 64bit LDD/STD"
403 Enable gcc to generate 64-bit load/store instructions
404 ISA mandates even/odd registers to allow encoding of two
405 dest operands with 2 possible source operands.
408 config ARC_HAS_DIV_REM
409 bool "Insn: div, divu, rem, remu"
413 bool "Local 64-bit r/o cycle counter"
418 bool "SMP synchronized 64-bit cycle counter"
422 config ARC_NUMBER_OF_INTERRUPTS
423 int "Number of interrupts"
427 This defines the number of interrupts on the ARCv2HS core.
428 It affects the size of vector table.
429 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
430 in hardware, it keep things simple for Linux to assume they are always
435 endmenu # "ARC CPU Configuration"
437 config LINUX_LINK_BASE
438 hex "Linux Link Address"
441 ARC700 divides the 32 bit phy address space into two equal halves
442 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
443 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
444 Typically Linux kernel is linked at the start of untransalted addr,
445 hence the default value of 0x8zs.
446 However some customers have peripherals mapped at this addr, so
447 Linux needs to be scooted a bit.
448 If you don't know what the above means, leave this setting alone.
449 This needs to match memory start address specified in Device Tree
452 bool "High Memory Support"
454 With ARC 2G:2G address split, only upper 2G is directly addressable by
455 kernel. Enable this to potentially allow access to rest of 2G and PAE
459 bool "Support for the 40-bit Physical Address Extension"
464 Enable access to physical memory beyond 4G, only supported on
465 ARC cores with 40 bit Physical Addressing support
467 config ARCH_PHYS_ADDR_T_64BIT
468 def_bool ARC_HAS_PAE40
470 config ARCH_DMA_ADDR_T_64BIT
473 config ARC_CURR_IN_REG
474 bool "Dedicate Register r25 for current_task pointer"
477 This reserved Register R25 to point to Current Task in
478 kernel mode. This saves memory access for each such access
481 config ARC_EMUL_UNALIGNED
482 bool "Emulate unaligned memory access (userspace only)"
484 select SYSCTL_ARCH_UNALIGN_NO_WARN
485 select SYSCTL_ARCH_UNALIGN_ALLOW
486 depends on ISA_ARCOMPACT
488 This enables misaligned 16 & 32 bit memory access from user space.
489 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
490 potential bugs in code
493 int "Timer Frequency"
496 config ARC_METAWARE_HLINK
497 bool "Support for Metaware debugger assisted Host access"
500 This options allows a Linux userland apps to directly access
501 host file system (open/creat/read/write etc) with help from
502 Metaware Debugger. This can come in handy for Linux-host communication
503 when there is no real usable peripheral such as EMAC.
511 config ARC_DW2_UNWIND
512 bool "Enable DWARF specific kernel stack unwind"
516 Compiles the kernel with DWARF unwind information and can be used
517 to get stack backtraces.
519 If you say Y here the resulting kernel image will be slightly larger
520 but not slower, and it will give very useful debugging information.
521 If you don't debug the kernel, you can say N, but we may not be able
522 to solve problems without frame unwind information
524 config ARC_DBG_TLB_PARANOIA
525 bool "Paranoia Checks in Low Level TLB Handlers"
528 config ARC_DBG_TLB_MISS_COUNT
529 bool "Profile TLB Misses"
533 Counts number of I and D TLB Misses and exports them via Debugfs
534 The counters can be cleared via Debugfs as well
539 bool "Debug Inter Core interrupts"
546 config ARC_UBOOT_SUPPORT
547 bool "Support uboot arg Handling"
550 ARC Linux by default checks for uboot provided args as pointers to
551 external cmdline or DTB. This however breaks in absence of uboot,
552 when booting from Metaware debugger directly, as the registers are
553 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
554 registers look like uboot args to kernel which then chokes.
555 So only enable the uboot arg checking/processing if users are sure
556 of uboot being in play.
558 config ARC_BUILTIN_DTB_NAME
559 string "Built in DTB"
561 Set the name of the DTB to embed in the vmlinux binary
562 Leaving it blank selects the minimal "skeleton" dtb
564 source "kernel/Kconfig.preempt"
566 menu "Executable file formats"
567 source "fs/Kconfig.binfmt"
570 endmenu # "ARC Architecture Configuration"
574 source "drivers/Kconfig"
579 bool "PCI support" if MIGHT_HAVE_PCI
581 PCI is the name of a bus system, i.e., the way the CPU talks to
582 the other stuff inside your box. Find out if your board/platform
585 Note: PCIe support for Synopsys Device will be available only
586 when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
592 source "drivers/pci/Kconfig"
593 source "drivers/pci/pcie/Kconfig"
598 source "arch/arc/Kconfig.debug"
599 source "security/Kconfig"
600 source "crypto/Kconfig"
602 source "kernel/power/Kconfig"