2 * Support for peripherals on the AXS10x mainboard
4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 compatible = "simple-bus";
16 ranges = <0x00000000 0xe0000000 0x10000000>;
17 interrupt-parent = <&mb_intc>;
21 compatible = "fixed-clock";
22 clock-frequency = <50000000>;
27 compatible = "fixed-clock";
28 clock-frequency = <50000000>;
33 compatible = "fixed-clock";
34 clock-frequency = <50000000>;
40 #interrupt-cells = <1>;
41 compatible = "snps,dwmac";
42 reg = < 0x18000 0x2000 >;
44 interrupt-names = "macirq";
48 clock-names = "stmmaceth";
53 compatible = "snps,dwmac-mdio";
54 phy1: ethernet-phy@1 {
61 compatible = "generic-ehci";
62 reg = < 0x40000 0x100 >;
67 compatible = "generic-ohci";
68 reg = < 0x60000 0x100 >;
73 * According to DW Mobile Storage databook it is required
74 * to use "Hold Register" if card is enumerated in SDR12 or
77 * Utilization of "Hold Register" is already implemented via
78 * dw_mci_pltfm_prepare_command() which in its turn gets
79 * used through dw_mci_drv_data->prepare_command call-back.
80 * This call-back is used in Altera Socfpga platform and so
81 * we may reuse it saying that we're compatible with their
82 * "altr,socfpga-dw-mshc".
84 * Most probably "Hold Register" utilization is platform-
85 * independent requirement which means that single unified
86 * "snps,dw-mshc" should be enough for all users of DW MMC once
87 * dw_mci_pltfm_prepare_command() is used in generic platform
91 compatible = "altr,socfpga-dw-mshc";
92 reg = < 0x15000 0x400 >;
95 card-detect-delay = < 200 >;
96 clocks = <&apbclk>, <&mmcclk>;
97 clock-names = "biu", "ciu";
103 compatible = "snps,dw-apb-uart";
104 reg = <0x20000 0x100>;
105 clock-frequency = <33333333>;
113 compatible = "snps,dw-apb-uart";
114 reg = <0x21000 0x100>;
115 clock-frequency = <33333333>;
122 /* UART muxed with USB data port (ttyS3) */
124 compatible = "snps,dw-apb-uart";
125 reg = <0x22000 0x100>;
126 clock-frequency = <33333333>;
134 compatible = "snps,designware-i2c";
135 reg = <0x1d000 0x100>;
136 clock-frequency = <400000>;
142 compatible = "snps,designware-i2c";
143 reg = <0x1e000 0x100>;
144 clock-frequency = <400000>;
150 compatible = "snps,designware-i2c";
151 #address-cells = <1>;
153 reg = <0x1f000 0x100>;
154 clock-frequency = <400000>;
159 compatible = "24c01";
165 compatible = "24c04";
172 compatible = "snps,dw-apb-gpio";
173 reg = <0x13000 0x1000>;
174 #address-cells = <1>;
177 gpio0_banka: gpio-controller@0 {
178 compatible = "snps,dw-apb-gpio-port";
181 snps,nr-gpios = <32>;
185 gpio0_bankb: gpio-controller@1 {
186 compatible = "snps,dw-apb-gpio-port";
193 gpio0_bankc: gpio-controller@2 {
194 compatible = "snps,dw-apb-gpio-port";
203 compatible = "snps,dw-apb-gpio";
204 reg = <0x14000 0x1000>;
205 #address-cells = <1>;
208 gpio1_banka: gpio-controller@0 {
209 compatible = "snps,dw-apb-gpio-port";
212 snps,nr-gpios = <30>;
216 gpio1_bankb: gpio-controller@1 {
217 compatible = "snps,dw-apb-gpio-port";
220 snps,nr-gpios = <10>;
224 gpio1_bankc: gpio-controller@2 {
225 compatible = "snps,dw-apb-gpio-port";