arch/arc/boot/dts/axs10x_mb.dtsi

   1 /*
   2  * Support for peripherals on the AXS10x mainboard
   3  *
   4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 / {
  12         axs10x_mb {
  13                 compatible = "simple-bus";
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges = <0x00000000 0xe0000000 0x10000000>;
  17                 interrupt-parent = <&mb_intc>;
  18
  19                 clocks {
  20                         i2cclk: i2cclk {
  21                                 compatible = "fixed-clock";
  22                                 clock-frequency = <50000000>;
  23                                 #clock-cells = <0>;
  24                         };
  25
  26                         apbclk: apbclk {
  27                                 compatible = "fixed-clock";
  28                                 clock-frequency = <50000000>;
  29                                 #clock-cells = <0>;
  30                         };
  31
  32                         mmcclk: mmcclk {
  33                                 compatible = "fixed-clock";
  34                                 clock-frequency = <50000000>;
  35                                 #clock-cells = <0>;
  36                         };
  37                 };
  38
  39                 ethernet@0x18000 {
  40                         #interrupt-cells = <1>;
  41                         compatible = "snps,dwmac";
  42                         reg = < 0x18000 0x2000 >;
  43                         interrupts = < 4 >;
  44                         interrupt-names = "macirq";
  45                         phy-mode = "rgmii";
  46                         snps,pbl = < 32 >;
  47                         clocks = <&apbclk>;
  48                         clock-names = "stmmaceth";
  49                         max-speed = <100>;
  50                         mdio0 {
  51                                 #address-cells = <1>;
  52                                 #size-cells = <0>;
  53                                 compatible = "snps,dwmac-mdio";
  54                                 phy1: ethernet-phy@1 {
  55                                         reg = <1>;
  56                                 };
  57                         };
  58                 };
  59
  60                 ehci@0x40000 {
  61                         compatible = "generic-ehci";
  62                         reg = < 0x40000 0x100 >;
  63                         interrupts = < 8 >;
  64                 };
  65
  66                 ohci@0x60000 {
  67                         compatible = "generic-ohci";
  68                         reg = < 0x60000 0x100 >;
  69                         interrupts = < 8 >;
  70                 };
  71
  72                 /*
  73                  * According to DW Mobile Storage databook it is required
  74                  * to use  "Hold Register" if card is enumerated in SDR12 or
  75                  * SDR25 modes.
  76                  *
  77                  * Utilization of "Hold Register" is already implemented via
  78                  * dw_mci_pltfm_prepare_command() which in its turn gets
  79                  * used through dw_mci_drv_data->prepare_command call-back.
  80                  * This call-back is used in Altera Socfpga platform and so
  81                  * we may reuse it saying that we're compatible with their
  82                  * "altr,socfpga-dw-mshc".
  83                  *
  84                  * Most probably "Hold Register" utilization is platform-
  85                  * independent requirement which means that single unified
  86                  * "snps,dw-mshc" should be enough for all users of DW MMC once
  87                  * dw_mci_pltfm_prepare_command() is used in generic platform
  88                  * code.
  89                  */
  90                 mmc@0x15000 {
  91                         compatible = "altr,socfpga-dw-mshc";
  92                         reg = < 0x15000 0x400 >;
  93                         num-slots = < 1 >;
  94                         fifo-depth = < 16 >;
  95                         card-detect-delay = < 200 >;
  96                         clocks = <&apbclk>, <&mmcclk>;
  97                         clock-names = "biu", "ciu";
  98                         interrupts = < 7 >;
  99                         bus-width = < 4 >;
 100                 };
 101
 102                 uart@0x20000 {
 103                         compatible = "snps,dw-apb-uart";
 104                         reg = <0x20000 0x100>;
 105                         clock-frequency = <33333333>;
 106                         interrupts = <17>;
 107                         baud = <115200>;
 108                         reg-shift = <2>;
 109                         reg-io-width = <4>;
 110                 };
 111
 112                 uart@0x21000 {
 113                         compatible = "snps,dw-apb-uart";
 114                         reg = <0x21000 0x100>;
 115                         clock-frequency = <33333333>;
 116                         interrupts = <18>;
 117                         baud = <115200>;
 118                         reg-shift = <2>;
 119                         reg-io-width = <4>;
 120                 };
 121
 122                 /* UART muxed with USB data port (ttyS3) */
 123                 uart@0x22000 {
 124                         compatible = "snps,dw-apb-uart";
 125                         reg = <0x22000 0x100>;
 126                         clock-frequency = <33333333>;
 127                         interrupts = <19>;
 128                         baud = <115200>;
 129                         reg-shift = <2>;
 130                         reg-io-width = <4>;
 131                 };
 132
 133                 i2c@0x1d000 {
 134                         compatible = "snps,designware-i2c";
 135                         reg = <0x1d000 0x100>;
 136                         clock-frequency = <400000>;
 137                         clocks = <&i2cclk>;
 138                         interrupts = <14>;
 139                 };
 140
 141                 i2c@0x1e000 {
 142                         compatible = "snps,designware-i2c";
 143                         reg = <0x1e000 0x100>;
 144                         clock-frequency = <400000>;
 145                         clocks = <&i2cclk>;
 146                         interrupts = <15>;
 147                 };
 148
 149                 i2c@0x1f000 {
 150                         compatible = "snps,designware-i2c";
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         reg = <0x1f000 0x100>;
 154                         clock-frequency = <400000>;
 155                         clocks = <&i2cclk>;
 156                         interrupts = <16>;
 157
 158                         eeprom@0x54{
 159                                 compatible = "24c01";
 160                                 reg = <0x54>;
 161                                 pagesize = <0x8>;
 162                         };
 163
 164                         eeprom@0x57{
 165                                 compatible = "24c04";
 166                                 reg = <0x57>;
 167                                 pagesize = <0x8>;
 168                         };
 169                 };
 170
 171                 gpio0:gpio@13000 {
 172                         compatible = "snps,dw-apb-gpio";
 173                         reg = <0x13000 0x1000>;
 174                         #address-cells = <1>;
 175                         #size-cells = <0>;
 176
 177                         gpio0_banka: gpio-controller@0 {
 178                                 compatible = "snps,dw-apb-gpio-port";
 179                                 gpio-controller;
 180                                 #gpio-cells = <2>;
 181                                 snps,nr-gpios = <32>;
 182                                 reg = <0>;
 183                         };
 184
 185                         gpio0_bankb: gpio-controller@1 {
 186                                 compatible = "snps,dw-apb-gpio-port";
 187                                 gpio-controller;
 188                                 #gpio-cells = <2>;
 189                                 snps,nr-gpios = <8>;
 190                                 reg = <1>;
 191                         };
 192
 193                         gpio0_bankc: gpio-controller@2 {
 194                                 compatible = "snps,dw-apb-gpio-port";
 195                                 gpio-controller;
 196                                 #gpio-cells = <2>;
 197                                 snps,nr-gpios = <8>;
 198                                 reg = <2>;
 199                         };
 200                 };
 201
 202                 gpio1:gpio@14000 {
 203                         compatible = "snps,dw-apb-gpio";
 204                         reg = <0x14000 0x1000>;
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207
 208                         gpio1_banka: gpio-controller@0 {
 209                                 compatible = "snps,dw-apb-gpio-port";
 210                                 gpio-controller;
 211                                 #gpio-cells = <2>;
 212                                 snps,nr-gpios = <30>;
 213                                 reg = <0>;
 214                         };
 215
 216                         gpio1_bankb: gpio-controller@1 {
 217                                 compatible = "snps,dw-apb-gpio-port";
 218                                 gpio-controller;
 219                                 #gpio-cells = <2>;
 220                                 snps,nr-gpios = <10>;
 221                                 reg = <1>;
 222                         };
 223
 224                         gpio1_bankc: gpio-controller@2 {
 225                                 compatible = "snps,dw-apb-gpio-port";
 226                                 gpio-controller;
 227                                 #gpio-cells = <2>;
 228                                 snps,nr-gpios = <8>;
 229                                 reg = <2>;
 230                         };
 231                 };
 232         };
 233 };