arch/arc/boot/dts/vdk_axc003.dtsi

   1 /*
   2  * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version)
  11  */
  12
  13 /include/ "skeleton_hs.dtsi"
  14
  15 / {
  16         compatible = "snps,arc";
  17         clock-frequency = <50000000>;
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         cpu_card {
  22                 compatible = "simple-bus";
  23                 #address-cells = <1>;
  24                 #size-cells = <1>;
  25
  26                 ranges = <0x00000000 0xf0000000 0x10000000>;
  27
  28                 core_clk: core_clk {
  29                         #clock-cells = <0>;
  30                         compatible = "fixed-clock";
  31                         clock-frequency = <50000000>;
  32                 };
  33
  34                 core_intc: archs-intc@cpu {
  35                         compatible = "snps,archs-intc";
  36                         interrupt-controller;
  37                         #interrupt-cells = <1>;
  38                 };
  39
  40                 debug_uart: dw-apb-uart@0x5000 {
  41                         compatible = "snps,dw-apb-uart";
  42                         reg = <0x5000 0x100>;
  43                         clock-frequency = <2403200>;
  44                         interrupt-parent = <&core_intc>;
  45                         interrupts = <19>;
  46                         baud = <115200>;
  47                         reg-shift = <2>;
  48                         reg-io-width = <4>;
  49                 };
  50
  51         };
  52
  53         mb_intc: dw-apb-ictl@0xe0012000 {
  54                 #interrupt-cells = <1>;
  55                 compatible = "snps,dw-apb-ictl";
  56                 reg = < 0xe0012000 0x200 >;
  57                 interrupt-controller;
  58                 interrupt-parent = <&core_intc>;
  59                 interrupts = < 18 >;
  60         };
  61
  62         memory {
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 ranges = <0x00000000 0x80000000 0x40000000>;
  66                 device_type = "memory";
  67                 reg = <0x80000000 0x20000000>;  /* 512MiB */
  68         };
  69 };