2 * ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/smp.h>
12 #include <linux/irq.h>
13 #include <linux/spinlock.h>
14 #include <asm/irqflags-arcv2.h>
16 #include <asm/setup.h>
19 #define SOFTIRQ_IRQ 21
21 static char smp_cpuinfo_buf[128];
22 static int idu_detected;
24 static DEFINE_RAW_SPINLOCK(mcip_lock);
26 static void mcip_setup_per_cpu(int cpu)
28 smp_ipi_irq_setup(cpu, IPI_IRQ);
29 smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ);
32 static void mcip_ipi_send(int cpu)
37 /* ARConnect can only send IPI to others */
38 if (unlikely(cpu == raw_smp_processor_id())) {
39 arc_softirq_trigger(SOFTIRQ_IRQ);
43 raw_spin_lock_irqsave(&mcip_lock, flags);
46 * If receiver already has a pending interrupt, elide sending this one.
47 * Linux cross core calling works well with concurrent IPIs
49 * see arch/arc/kernel/smp.c: ipi_send_msg_one()
51 __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
52 ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
54 __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
56 raw_spin_unlock_irqrestore(&mcip_lock, flags);
59 static void mcip_ipi_clear(int irq)
64 if (unlikely(irq == SOFTIRQ_IRQ)) {
65 arc_softirq_clear(irq);
69 raw_spin_lock_irqsave(&mcip_lock, flags);
71 /* Who sent the IPI */
72 __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);
74 cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */
77 * In rare case, multiple concurrent IPIs sent to same target can
78 * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be
79 * "vectored" (multiple bits sets) as opposed to typical single bit
82 c = __ffs(cpu); /* 0,1,2,3 */
83 __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c);
87 raw_spin_unlock_irqrestore(&mcip_lock, flags);
90 static void mcip_probe_n_setup(void)
93 #ifdef CONFIG_CPU_BIG_ENDIAN
95 idu:1, llm:1, num_cores:6,
96 iocoh:1, gfrc:1, dbg:1, pad2:1,
97 msg:1, sem:1, ipi:1, pad:1,
101 pad:1, ipi:1, sem:1, msg:1,
102 pad2:1, dbg:1, gfrc:1, iocoh:1,
103 num_cores:6, llm:1, idu:1,
108 READ_BCR(ARC_REG_MCIP_BCR, mp);
110 sprintf(smp_cpuinfo_buf,
111 "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n",
112 mp.ver, mp.num_cores,
113 IS_AVAIL1(mp.ipi, "IPI "),
114 IS_AVAIL1(mp.idu, "IDU "),
115 IS_AVAIL1(mp.llm, "LLM "),
116 IS_AVAIL1(mp.dbg, "DEBUG "),
117 IS_AVAIL1(mp.gfrc, "GFRC"));
119 cpuinfo_arc700[0].extn.gfrc = mp.gfrc;
120 idu_detected = mp.idu;
123 __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
124 __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
128 struct plat_smp_ops plat_smp_ops = {
129 .info = smp_cpuinfo_buf,
130 .init_early_smp = mcip_probe_n_setup,
131 .init_per_cpu = mcip_setup_per_cpu,
132 .ipi_send = mcip_ipi_send,
133 .ipi_clear = mcip_ipi_clear,
136 /***************************************************************************
137 * ARCv2 Interrupt Distribution Unit (IDU)
139 * Connects external "COMMON" IRQs to core intc, providing:
140 * -dynamic routing (IRQ affinity)
141 * -load balancing (Round Robin interrupt distribution)
144 * It physically resides in the MCIP hw block
147 #include <linux/irqchip.h>
148 #include <linux/of.h>
149 #include <linux/of_irq.h>
152 * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core)
154 static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
156 __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
159 static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
165 unsigned int distr:2, pad:2, lvl:1, pad2:27;
171 __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
174 static void idu_irq_mask(struct irq_data *data)
178 raw_spin_lock_irqsave(&mcip_lock, flags);
179 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
180 raw_spin_unlock_irqrestore(&mcip_lock, flags);
183 static void idu_irq_unmask(struct irq_data *data)
187 raw_spin_lock_irqsave(&mcip_lock, flags);
188 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);
189 raw_spin_unlock_irqrestore(&mcip_lock, flags);
194 idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
200 /* errout if no online cpu per @cpumask */
201 if (!cpumask_and(&online, cpumask, cpu_online_mask))
204 raw_spin_lock_irqsave(&mcip_lock, flags);
206 idu_set_dest(data->hwirq, cpumask_bits(&online)[0]);
207 idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
209 raw_spin_unlock_irqrestore(&mcip_lock, flags);
211 return IRQ_SET_MASK_OK;
215 static struct irq_chip idu_irq_chip = {
216 .name = "MCIP IDU Intc",
217 .irq_mask = idu_irq_mask,
218 .irq_unmask = idu_irq_unmask,
220 .irq_set_affinity = idu_irq_set_affinity,
225 static int idu_first_irq;
227 static void idu_cascade_isr(struct irq_desc *desc)
229 struct irq_domain *domain = irq_desc_get_handler_data(desc);
230 unsigned int core_irq = irq_desc_get_irq(desc);
231 unsigned int idu_irq;
233 idu_irq = core_irq - idu_first_irq;
234 generic_handle_irq(irq_find_mapping(domain, idu_irq));
237 static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
239 irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq);
240 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
245 static int idu_irq_xlate(struct irq_domain *d, struct device_node *n,
246 const u32 *intspec, unsigned int intsize,
247 irq_hw_number_t *out_hwirq, unsigned int *out_type)
249 irq_hw_number_t hwirq = *out_hwirq = intspec[0];
250 int distri = intspec[1];
253 *out_type = IRQ_TYPE_NONE;
255 /* XXX: validate distribution scheme again online cpu mask */
257 /* 0 - Round Robin to all cpus, otherwise 1 bit per core */
258 raw_spin_lock_irqsave(&mcip_lock, flags);
259 idu_set_dest(hwirq, BIT(num_online_cpus()) - 1);
260 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
261 raw_spin_unlock_irqrestore(&mcip_lock, flags);
264 * DEST based distribution for Level Triggered intr can only
265 * have 1 CPU, so generalize it to always contain 1 cpu
267 int cpu = ffs(distri);
269 if (cpu != fls(distri))
270 pr_warn("IDU irq %lx distri mode set to cpu %x\n",
273 raw_spin_lock_irqsave(&mcip_lock, flags);
274 idu_set_dest(hwirq, cpu);
275 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST);
276 raw_spin_unlock_irqrestore(&mcip_lock, flags);
282 static const struct irq_domain_ops idu_irq_ops = {
283 .xlate = idu_irq_xlate,
288 * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
289 * [24, 23+C]: If C > 0 then "C" common IRQs
290 * [24+C, N]: Not statically assigned, private-per-core
295 idu_of_init(struct device_node *intc, struct device_node *parent)
297 struct irq_domain *domain;
298 /* Read IDU BCR to confirm nr_irqs */
299 int nr_irqs = of_irq_count(intc);
303 panic("IDU not detected, but DeviceTree using it");
305 pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
307 domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
309 /* Parent interrupts (core-intc) are already mapped */
311 for (i = 0; i < nr_irqs; i++) {
313 * Return parent uplink IRQs (towards core intc) 24,25,.....
314 * this step has been done before already
315 * however we need it to get the parent virq and set IDU handler
318 irq = irq_of_parse_and_map(intc, i);
322 irq_set_chained_handler_and_data(irq, idu_cascade_isr, domain);
325 __mcip_cmd(CMD_IDU_ENABLE, 0);
329 IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);