4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_SCHED_CLOCK
24 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER
27 select HARDIRQS_SW_RESEND
28 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
31 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
32 select HAVE_ARCH_TRACEHOOK
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_CONTEXT_TRACKING
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_DEBUG_KMEMLEAK
38 select HAVE_DMA_API_DEBUG
40 select HAVE_DMA_CONTIGUOUS if MMU
41 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
42 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
43 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
44 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
45 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
46 select HAVE_GENERIC_DMA_COHERENT
47 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
48 select HAVE_IDE if PCI || ISA || PCMCIA
49 select HAVE_IRQ_TIME_ACCOUNTING
50 select HAVE_KERNEL_GZIP
51 select HAVE_KERNEL_LZ4
52 select HAVE_KERNEL_LZMA
53 select HAVE_KERNEL_LZO
55 select HAVE_KPROBES if !XIP_KERNEL
56 select HAVE_KRETPROBES if (HAVE_KPROBES)
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
60 select HAVE_PERF_EVENTS
62 select HAVE_PERF_USER_STACK_DUMP
63 select HAVE_REGS_AND_STACK_ACCESS_API
64 select HAVE_SYSCALL_TRACEPOINTS
66 select HAVE_VIRT_CPU_ACCOUNTING_GEN
67 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_XCHGADD_ALGORITHM
172 config ARCH_HAS_ILOG2_U32
175 config ARCH_HAS_ILOG2_U64
178 config ARCH_HAS_BANDGAP
181 config GENERIC_HWEIGHT
185 config GENERIC_CALIBRATE_DELAY
189 config ARCH_MAY_HAVE_PC_FDC
195 config NEED_DMA_MAP_STATE
198 config ARCH_SUPPORTS_UPROBES
201 config ARCH_HAS_DMA_SET_COHERENT_MASK
204 config GENERIC_ISA_DMA
210 config NEED_RET_TO_USER
218 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
219 default DRAM_BASE if REMAP_VECTORS_TO_RAM
222 The base address of exception vectors. This must be two pages
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
228 depends on !XIP_KERNEL && MMU
229 depends on !ARCH_REALVIEW || !SPARSEMEM
231 Patch phys-to-virt and virt-to-phys translation functions at
232 boot and module load time according to the position of the
233 kernel in system memory.
235 This can only be used with non-XIP MMU kernels where the base
236 of physical memory is at a 16MB boundary.
238 Only disable this option if you know that you do not require
239 this feature (eg, building a kernel for a single machine) and
240 you need to shrink the kernel to the minimal size.
242 config NEED_MACH_IO_H
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT
259 default DRAM_BASE if !MMU
260 default 0x00000000 if ARCH_EBSA110 || \
261 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
266 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
267 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
268 default 0x20000000 if ARCH_S5PV210
269 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
270 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
271 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
272 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
273 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
275 Please provide the physical address corresponding to the
276 location of main memory in your system.
282 source "init/Kconfig"
284 source "kernel/Kconfig.freezer"
289 bool "MMU-based Paged Memory Management Support"
292 Select if you want MMU-based virtualised addressing space
293 support by paged memory management. If unsure, say 'Y'.
296 # The "ARM system type" choice list is ordered alphabetically by option
297 # text. Please add new entries in the option alphabetic order.
300 prompt "ARM system type"
301 default ARCH_VERSATILE if !MMU
302 default ARCH_MULTIPLATFORM if MMU
304 config ARCH_MULTIPLATFORM
305 bool "Allow multiple platforms to be selected"
307 select ARCH_WANT_OPTIONAL_GPIOLIB
308 select ARM_HAS_SG_CHAIN
309 select ARM_PATCH_PHYS_VIRT
313 select GENERIC_CLOCKEVENTS
314 select MIGHT_HAVE_PCI
315 select MULTI_IRQ_HANDLER
319 config ARCH_INTEGRATOR
320 bool "ARM Ltd. Integrator family"
322 select ARM_PATCH_PHYS_VIRT if MMU
325 select COMMON_CLK_VERSATILE
326 select GENERIC_CLOCKEVENTS
329 select MULTI_IRQ_HANDLER
330 select PLAT_VERSATILE
333 select VERSATILE_FPGA_IRQ
335 Support for ARM's Integrator platform.
338 bool "ARM Ltd. RealView family"
339 select ARCH_WANT_OPTIONAL_GPIOLIB
341 select ARM_TIMER_SP804
343 select COMMON_CLK_VERSATILE
344 select GENERIC_CLOCKEVENTS
345 select GPIO_PL061 if GPIOLIB
347 select NEED_MACH_MEMORY_H
348 select PLAT_VERSATILE
350 This enables support for ARM Ltd RealView boards.
352 config ARCH_VERSATILE
353 bool "ARM Ltd. Versatile family"
354 select ARCH_WANT_OPTIONAL_GPIOLIB
356 select ARM_TIMER_SP804
359 select GENERIC_CLOCKEVENTS
360 select HAVE_MACH_CLKDEV
362 select PLAT_VERSATILE
363 select PLAT_VERSATILE_CLOCK
364 select VERSATILE_FPGA_IRQ
366 This enables support for ARM Ltd Versatile board.
370 select ARCH_REQUIRE_GPIOLIB
373 select NEED_MACH_IO_H if PCCARD
375 select PINCTRL_AT91 if USE_OF
377 This enables support for systems based on Atmel
378 AT91RM9200 and AT91SAM9* processors.
381 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
382 select ARCH_REQUIRE_GPIOLIB
387 select GENERIC_CLOCKEVENTS
390 Support for Cirrus Logic 711x/721x/731x based boards.
393 bool "Cortina Systems Gemini"
394 select ARCH_REQUIRE_GPIOLIB
397 select GENERIC_CLOCKEVENTS
399 Support for the Cortina Systems Gemini family SoCs
403 select ARCH_USES_GETTIMEOFFSET
406 select NEED_MACH_IO_H
407 select NEED_MACH_MEMORY_H
410 This is an evaluation board for the StrongARM processor available
411 from Digital. It has limited hardware on-board, including an
412 Ethernet interface, two PCMCIA sockets, two serial ports and a
416 bool "Energy Micro efm32"
418 select ARCH_REQUIRE_GPIOLIB
424 select GENERIC_CLOCKEVENTS
430 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
435 select ARCH_HAS_HOLES_MEMORYMODEL
436 select ARCH_REQUIRE_GPIOLIB
437 select ARCH_USES_GETTIMEOFFSET
443 This enables support for the Cirrus EP93xx series of CPUs.
445 config ARCH_FOOTBRIDGE
449 select GENERIC_CLOCKEVENTS
451 select NEED_MACH_IO_H if !MMU
452 select NEED_MACH_MEMORY_H
454 Support for systems based on the DC21285 companion chip
455 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
458 bool "Hilscher NetX based"
462 select GENERIC_CLOCKEVENTS
464 This enables support for systems based on the Hilscher NetX Soc
470 select NEED_MACH_MEMORY_H
471 select NEED_RET_TO_USER
477 Support for Intel's IOP13XX (XScale) family of processors.
482 select ARCH_REQUIRE_GPIOLIB
485 select NEED_RET_TO_USER
489 Support for Intel's 80219 and IOP32X (XScale) family of
495 select ARCH_REQUIRE_GPIOLIB
498 select NEED_RET_TO_USER
502 Support for Intel's IOP33X (XScale) family of processors.
507 select ARCH_HAS_DMA_SET_COHERENT_MASK
508 select ARCH_REQUIRE_GPIOLIB
509 select ARCH_SUPPORTS_BIG_ENDIAN
512 select DMABOUNCE if PCI
513 select GENERIC_CLOCKEVENTS
514 select MIGHT_HAVE_PCI
515 select NEED_MACH_IO_H
516 select USB_EHCI_BIG_ENDIAN_DESC
517 select USB_EHCI_BIG_ENDIAN_MMIO
519 Support for Intel's IXP4XX (XScale) family of processors.
523 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
526 select MIGHT_HAVE_PCI
530 select PLAT_ORION_LEGACY
532 Support for the Marvell Dove SoC 88AP510
535 bool "Marvell Kirkwood"
536 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
543 select PINCTRL_KIRKWOOD
544 select PLAT_ORION_LEGACY
546 Support for the following Marvell Kirkwood series SoCs:
547 88F6180, 88F6192 and 88F6281.
550 bool "Marvell MV78xx0"
551 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_CLOCKEVENTS
556 select PLAT_ORION_LEGACY
558 Support for the following Marvell MV78xx0 series SoCs:
564 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_CLOCKEVENTS
569 select PLAT_ORION_LEGACY
571 Support for the following Marvell Orion 5x series SoCs:
572 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
573 Orion-2 (5281), Orion-1-90 (6183).
576 bool "Marvell PXA168/910/MMP2"
578 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_ALLOCATOR
581 select GENERIC_CLOCKEVENTS
584 select MULTI_IRQ_HANDLER
589 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
592 bool "Micrel/Kendin KS8695"
593 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
597 select NEED_MACH_MEMORY_H
599 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
600 System-on-Chip devices.
603 bool "Nuvoton W90X900 CPU"
604 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_CLOCKEVENTS
610 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
611 At present, the w90x900 has been renamed nuc900, regarding
612 the ARM series product line, you can login the following
613 link address to know more.
615 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
616 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
620 select ARCH_REQUIRE_GPIOLIB
625 select GENERIC_CLOCKEVENTS
629 Support for the NXP LPC32XX family of processors
632 bool "PXA2xx/PXA3xx-based"
635 select ARCH_REQUIRE_GPIOLIB
636 select ARM_CPU_SUSPEND if PM
641 select GENERIC_CLOCKEVENTS
644 select MULTI_IRQ_HANDLER
648 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
651 bool "Qualcomm MSM (non-multiplatform)"
652 select ARCH_REQUIRE_GPIOLIB
654 select GENERIC_CLOCKEVENTS
656 Support for Qualcomm MSM/QSD based systems. This runs on the
657 apps processor of the MSM/QSD and depends on a shared memory
658 interface to the modem processor which runs the baseband
659 stack and controls some vital subsystems
660 (clock and power control, etc).
662 config ARCH_SHMOBILE_LEGACY
663 bool "Renesas ARM SoCs (non-multiplatform)"
665 select ARM_PATCH_PHYS_VIRT if MMU
667 select GENERIC_CLOCKEVENTS
668 select HAVE_ARM_SCU if SMP
669 select HAVE_ARM_TWD if SMP
670 select HAVE_MACH_CLKDEV
672 select MIGHT_HAVE_CACHE_L2X0
673 select MULTI_IRQ_HANDLER
676 select PM_GENERIC_DOMAINS if PM
679 Support for Renesas ARM SoC platforms using a non-multiplatform
680 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
686 select ARCH_MAY_HAVE_PC_FDC
687 select ARCH_SPARSEMEM_ENABLE
688 select ARCH_USES_GETTIMEOFFSET
692 select HAVE_PATA_PLATFORM
694 select NEED_MACH_IO_H
695 select NEED_MACH_MEMORY_H
699 On the Acorn Risc-PC, Linux can support the internal IDE disk and
700 CD-ROM interface, serial and parallel port, and the floppy drive.
705 select ARCH_REQUIRE_GPIOLIB
706 select ARCH_SPARSEMEM_ENABLE
711 select GENERIC_CLOCKEVENTS
714 select NEED_MACH_MEMORY_H
717 Support for StrongARM 11x0 based boards.
720 bool "Samsung S3C24XX SoCs"
721 select ARCH_REQUIRE_GPIOLIB
724 select CLKSRC_SAMSUNG_PWM
725 select GENERIC_CLOCKEVENTS
727 select HAVE_S3C2410_I2C if I2C
728 select HAVE_S3C2410_WATCHDOG if WATCHDOG
729 select HAVE_S3C_RTC if RTC_CLASS
730 select MULTI_IRQ_HANDLER
731 select NEED_MACH_IO_H
734 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
735 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
736 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
737 Samsung SMDK2410 development board (and derivatives).
740 bool "Samsung S3C64XX"
741 select ARCH_REQUIRE_GPIOLIB
746 select CLKSRC_SAMSUNG_PWM
747 select COMMON_CLK_SAMSUNG
749 select GENERIC_CLOCKEVENTS
751 select HAVE_S3C2410_I2C if I2C
752 select HAVE_S3C2410_WATCHDOG if WATCHDOG
756 select PM_GENERIC_DOMAINS if PM
758 select S3C_GPIO_TRACK
760 select SAMSUNG_WAKEMASK
761 select SAMSUNG_WDT_RESET
763 Samsung S3C64XX series based systems
766 bool "Samsung S5PV210/S5PC110"
767 select ARCH_HAS_HOLES_MEMORYMODEL
768 select ARCH_SPARSEMEM_ENABLE
771 select CLKSRC_SAMSUNG_PWM
773 select GENERIC_CLOCKEVENTS
775 select HAVE_S3C2410_I2C if I2C
776 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 select HAVE_S3C_RTC if RTC_CLASS
778 select NEED_MACH_MEMORY_H
781 Samsung S5PV210/S5PC110 series based systems
785 select ARCH_HAS_HOLES_MEMORYMODEL
786 select ARCH_REQUIRE_GPIOLIB
788 select GENERIC_ALLOCATOR
789 select GENERIC_CLOCKEVENTS
790 select GENERIC_IRQ_CHIP
796 Support for TI's DaVinci platform.
801 select ARCH_HAS_HOLES_MEMORYMODEL
803 select ARCH_REQUIRE_GPIOLIB
806 select GENERIC_CLOCKEVENTS
807 select GENERIC_IRQ_CHIP
810 select NEED_MACH_IO_H if PCCARD
811 select NEED_MACH_MEMORY_H
813 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
817 menu "Multiple platform selection"
818 depends on ARCH_MULTIPLATFORM
820 comment "CPU Core family selection"
823 bool "ARMv4 based platforms (FA526)"
824 depends on !ARCH_MULTI_V6_V7
825 select ARCH_MULTI_V4_V5
828 config ARCH_MULTI_V4T
829 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
830 depends on !ARCH_MULTI_V6_V7
831 select ARCH_MULTI_V4_V5
832 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
833 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
834 CPU_ARM925T || CPU_ARM940T)
837 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
838 depends on !ARCH_MULTI_V6_V7
839 select ARCH_MULTI_V4_V5
840 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
841 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
842 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
844 config ARCH_MULTI_V4_V5
848 bool "ARMv6 based platforms (ARM11)"
849 select ARCH_MULTI_V6_V7
853 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
855 select ARCH_MULTI_V6_V7
859 config ARCH_MULTI_V6_V7
861 select MIGHT_HAVE_CACHE_L2X0
863 config ARCH_MULTI_CPU_AUTO
864 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
870 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
874 select HAVE_ARM_ARCH_TIMER
877 # This is sorted alphabetically by mach-* pathname. However, plat-*
878 # Kconfigs may be included either alphabetically (according to the
879 # plat- suffix) or along side the corresponding mach-* source.
881 source "arch/arm/mach-mvebu/Kconfig"
883 source "arch/arm/mach-at91/Kconfig"
885 source "arch/arm/mach-axxia/Kconfig"
887 source "arch/arm/mach-bcm/Kconfig"
889 source "arch/arm/mach-berlin/Kconfig"
891 source "arch/arm/mach-clps711x/Kconfig"
893 source "arch/arm/mach-cns3xxx/Kconfig"
895 source "arch/arm/mach-davinci/Kconfig"
897 source "arch/arm/mach-dove/Kconfig"
899 source "arch/arm/mach-ep93xx/Kconfig"
901 source "arch/arm/mach-footbridge/Kconfig"
903 source "arch/arm/mach-gemini/Kconfig"
905 source "arch/arm/mach-highbank/Kconfig"
907 source "arch/arm/mach-hisi/Kconfig"
909 source "arch/arm/mach-integrator/Kconfig"
911 source "arch/arm/mach-iop32x/Kconfig"
913 source "arch/arm/mach-iop33x/Kconfig"
915 source "arch/arm/mach-iop13xx/Kconfig"
917 source "arch/arm/mach-ixp4xx/Kconfig"
919 source "arch/arm/mach-keystone/Kconfig"
921 source "arch/arm/mach-kirkwood/Kconfig"
923 source "arch/arm/mach-ks8695/Kconfig"
925 source "arch/arm/mach-msm/Kconfig"
927 source "arch/arm/mach-moxart/Kconfig"
929 source "arch/arm/mach-mv78xx0/Kconfig"
931 source "arch/arm/mach-imx/Kconfig"
933 source "arch/arm/mach-mxs/Kconfig"
935 source "arch/arm/mach-netx/Kconfig"
937 source "arch/arm/mach-nomadik/Kconfig"
939 source "arch/arm/mach-nspire/Kconfig"
941 source "arch/arm/plat-omap/Kconfig"
943 source "arch/arm/mach-omap1/Kconfig"
945 source "arch/arm/mach-omap2/Kconfig"
947 source "arch/arm/mach-orion5x/Kconfig"
949 source "arch/arm/mach-picoxcell/Kconfig"
951 source "arch/arm/mach-pxa/Kconfig"
952 source "arch/arm/plat-pxa/Kconfig"
954 source "arch/arm/mach-mmp/Kconfig"
956 source "arch/arm/mach-qcom/Kconfig"
958 source "arch/arm/mach-realview/Kconfig"
960 source "arch/arm/mach-rockchip/Kconfig"
962 source "arch/arm/mach-sa1100/Kconfig"
964 source "arch/arm/mach-socfpga/Kconfig"
966 source "arch/arm/mach-spear/Kconfig"
968 source "arch/arm/mach-sti/Kconfig"
970 source "arch/arm/mach-s3c24xx/Kconfig"
972 source "arch/arm/mach-s3c64xx/Kconfig"
974 source "arch/arm/mach-s5pv210/Kconfig"
976 source "arch/arm/mach-exynos/Kconfig"
977 source "arch/arm/plat-samsung/Kconfig"
979 source "arch/arm/mach-shmobile/Kconfig"
981 source "arch/arm/mach-sunxi/Kconfig"
983 source "arch/arm/mach-prima2/Kconfig"
985 source "arch/arm/mach-tegra/Kconfig"
987 source "arch/arm/mach-u300/Kconfig"
989 source "arch/arm/mach-ux500/Kconfig"
991 source "arch/arm/mach-versatile/Kconfig"
993 source "arch/arm/mach-vexpress/Kconfig"
994 source "arch/arm/plat-versatile/Kconfig"
996 source "arch/arm/mach-vt8500/Kconfig"
998 source "arch/arm/mach-w90x900/Kconfig"
1000 source "arch/arm/mach-zynq/Kconfig"
1002 # Definitions to make life easier
1008 select GENERIC_CLOCKEVENTS
1014 select GENERIC_IRQ_CHIP
1017 config PLAT_ORION_LEGACY
1024 config PLAT_VERSATILE
1027 config ARM_TIMER_SP804
1030 select CLKSRC_OF if OF
1032 source "arch/arm/firmware/Kconfig"
1034 source arch/arm/mm/Kconfig
1037 bool "Enable iWMMXt support"
1038 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1039 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1041 Enable support for iWMMXt context switching at run time if
1042 running on a CPU that supports it.
1044 config MULTI_IRQ_HANDLER
1047 Allow each machine to specify it's own IRQ handler at run time.
1050 source "arch/arm/Kconfig-nommu"
1053 config PJ4B_ERRATA_4742
1054 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1055 depends on CPU_PJ4B && MACH_ARMADA_370
1058 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1059 Event (WFE) IDLE states, a specific timing sensitivity exists between
1060 the retiring WFI/WFE instructions and the newly issued subsequent
1061 instructions. This sensitivity can result in a CPU hang scenario.
1063 The software must insert either a Data Synchronization Barrier (DSB)
1064 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1067 config ARM_ERRATA_326103
1068 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1071 Executing a SWP instruction to read-only memory does not set bit 11
1072 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1073 treat the access as a read, preventing a COW from occurring and
1074 causing the faulting task to livelock.
1076 config ARM_ERRATA_411920
1077 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1078 depends on CPU_V6 || CPU_V6K
1080 Invalidation of the Instruction Cache operation can
1081 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1082 It does not affect the MPCore. This option enables the ARM Ltd.
1083 recommended workaround.
1085 config ARM_ERRATA_430973
1086 bool "ARM errata: Stale prediction on replaced interworking branch"
1089 This option enables the workaround for the 430973 Cortex-A8
1090 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1091 interworking branch is replaced with another code sequence at the
1092 same virtual address, whether due to self-modifying code or virtual
1093 to physical address re-mapping, Cortex-A8 does not recover from the
1094 stale interworking branch prediction. This results in Cortex-A8
1095 executing the new code sequence in the incorrect ARM or Thumb state.
1096 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1097 and also flushes the branch target cache at every context switch.
1098 Note that setting specific bits in the ACTLR register may not be
1099 available in non-secure mode.
1101 config ARM_ERRATA_458693
1102 bool "ARM errata: Processor deadlock when a false hazard is created"
1104 depends on !ARCH_MULTIPLATFORM
1106 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1107 erratum. For very specific sequences of memory operations, it is
1108 possible for a hazard condition intended for a cache line to instead
1109 be incorrectly associated with a different cache line. This false
1110 hazard might then cause a processor deadlock. The workaround enables
1111 the L1 caching of the NEON accesses and disables the PLD instruction
1112 in the ACTLR register. Note that setting specific bits in the ACTLR
1113 register may not be available in non-secure mode.
1115 config ARM_ERRATA_460075
1116 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1118 depends on !ARCH_MULTIPLATFORM
1120 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1121 erratum. Any asynchronous access to the L2 cache may encounter a
1122 situation in which recent store transactions to the L2 cache are lost
1123 and overwritten with stale memory contents from external memory. The
1124 workaround disables the write-allocate mode for the L2 cache via the
1125 ACTLR register. Note that setting specific bits in the ACTLR register
1126 may not be available in non-secure mode.
1128 config ARM_ERRATA_742230
1129 bool "ARM errata: DMB operation may be faulty"
1130 depends on CPU_V7 && SMP
1131 depends on !ARCH_MULTIPLATFORM
1133 This option enables the workaround for the 742230 Cortex-A9
1134 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1135 between two write operations may not ensure the correct visibility
1136 ordering of the two writes. This workaround sets a specific bit in
1137 the diagnostic register of the Cortex-A9 which causes the DMB
1138 instruction to behave as a DSB, ensuring the correct behaviour of
1141 config ARM_ERRATA_742231
1142 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1143 depends on CPU_V7 && SMP
1144 depends on !ARCH_MULTIPLATFORM
1146 This option enables the workaround for the 742231 Cortex-A9
1147 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1148 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1149 accessing some data located in the same cache line, may get corrupted
1150 data due to bad handling of the address hazard when the line gets
1151 replaced from one of the CPUs at the same time as another CPU is
1152 accessing it. This workaround sets specific bits in the diagnostic
1153 register of the Cortex-A9 which reduces the linefill issuing
1154 capabilities of the processor.
1156 config ARM_ERRATA_643719
1157 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1158 depends on CPU_V7 && SMP
1160 This option enables the workaround for the 643719 Cortex-A9 (prior to
1161 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1162 register returns zero when it should return one. The workaround
1163 corrects this value, ensuring cache maintenance operations which use
1164 it behave as intended and avoiding data corruption.
1166 config ARM_ERRATA_720789
1167 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1170 This option enables the workaround for the 720789 Cortex-A9 (prior to
1171 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1172 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1173 As a consequence of this erratum, some TLB entries which should be
1174 invalidated are not, resulting in an incoherency in the system page
1175 tables. The workaround changes the TLB flushing routines to invalidate
1176 entries regardless of the ASID.
1178 config ARM_ERRATA_743622
1179 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1181 depends on !ARCH_MULTIPLATFORM
1183 This option enables the workaround for the 743622 Cortex-A9
1184 (r2p*) erratum. Under very rare conditions, a faulty
1185 optimisation in the Cortex-A9 Store Buffer may lead to data
1186 corruption. This workaround sets a specific bit in the diagnostic
1187 register of the Cortex-A9 which disables the Store Buffer
1188 optimisation, preventing the defect from occurring. This has no
1189 visible impact on the overall performance or power consumption of the
1192 config ARM_ERRATA_751472
1193 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1195 depends on !ARCH_MULTIPLATFORM
1197 This option enables the workaround for the 751472 Cortex-A9 (prior
1198 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1199 completion of a following broadcasted operation if the second
1200 operation is received by a CPU before the ICIALLUIS has completed,
1201 potentially leading to corrupted entries in the cache or TLB.
1203 config ARM_ERRATA_754322
1204 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1207 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1208 r3p*) erratum. A speculative memory access may cause a page table walk
1209 which starts prior to an ASID switch but completes afterwards. This
1210 can populate the micro-TLB with a stale entry which may be hit with
1211 the new ASID. This workaround places two dsb instructions in the mm
1212 switching code so that no page table walks can cross the ASID switch.
1214 config ARM_ERRATA_754327
1215 bool "ARM errata: no automatic Store Buffer drain"
1216 depends on CPU_V7 && SMP
1218 This option enables the workaround for the 754327 Cortex-A9 (prior to
1219 r2p0) erratum. The Store Buffer does not have any automatic draining
1220 mechanism and therefore a livelock may occur if an external agent
1221 continuously polls a memory location waiting to observe an update.
1222 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1223 written polling loops from denying visibility of updates to memory.
1225 config ARM_ERRATA_364296
1226 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1229 This options enables the workaround for the 364296 ARM1136
1230 r0p2 erratum (possible cache data corruption with
1231 hit-under-miss enabled). It sets the undocumented bit 31 in
1232 the auxiliary control register and the FI bit in the control
1233 register, thus disabling hit-under-miss without putting the
1234 processor into full low interrupt latency mode. ARM11MPCore
1237 config ARM_ERRATA_764369
1238 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1239 depends on CPU_V7 && SMP
1241 This option enables the workaround for erratum 764369
1242 affecting Cortex-A9 MPCore with two or more processors (all
1243 current revisions). Under certain timing circumstances, a data
1244 cache line maintenance operation by MVA targeting an Inner
1245 Shareable memory region may fail to proceed up to either the
1246 Point of Coherency or to the Point of Unification of the
1247 system. This workaround adds a DSB instruction before the
1248 relevant cache maintenance functions and sets a specific bit
1249 in the diagnostic control register of the SCU.
1251 config ARM_ERRATA_775420
1252 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1255 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1256 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1257 operation aborts with MMU exception, it might cause the processor
1258 to deadlock. This workaround puts DSB before executing ISB if
1259 an abort may occur on cache maintenance.
1261 config ARM_ERRATA_798181
1262 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1263 depends on CPU_V7 && SMP
1265 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1266 adequately shooting down all use of the old entries. This
1267 option enables the Linux kernel workaround for this erratum
1268 which sends an IPI to the CPUs that are running the same ASID
1269 as the one being invalidated.
1271 config ARM_ERRATA_773022
1272 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1275 This option enables the workaround for the 773022 Cortex-A15
1276 (up to r0p4) erratum. In certain rare sequences of code, the
1277 loop buffer may deliver incorrect instructions. This
1278 workaround disables the loop buffer to avoid the erratum.
1282 source "arch/arm/common/Kconfig"
1292 Find out whether you have ISA slots on your motherboard. ISA is the
1293 name of a bus system, i.e. the way the CPU talks to the other stuff
1294 inside your box. Other bus systems are PCI, EISA, MicroChannel
1295 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1296 newer boards don't support it. If you have ISA, say Y, otherwise N.
1298 # Select ISA DMA controller support
1303 # Select ISA DMA interface
1308 bool "PCI support" if MIGHT_HAVE_PCI
1310 Find out whether you have a PCI motherboard. PCI is the name of a
1311 bus system, i.e. the way the CPU talks to the other stuff inside
1312 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1313 VESA. If you have PCI, say Y, otherwise N.
1319 config PCI_NANOENGINE
1320 bool "BSE nanoEngine PCI support"
1321 depends on SA1100_NANOENGINE
1323 Enable PCI on the BSE nanoEngine board.
1328 config PCI_HOST_ITE8152
1330 depends on PCI && MACH_ARMCORE
1334 source "drivers/pci/Kconfig"
1335 source "drivers/pci/pcie/Kconfig"
1337 source "drivers/pcmcia/Kconfig"
1341 menu "Kernel Features"
1346 This option should be selected by machines which have an SMP-
1349 The only effect of this option is to make the SMP-related
1350 options available to the user for configuration.
1353 bool "Symmetric Multi-Processing"
1354 depends on CPU_V6K || CPU_V7
1355 depends on GENERIC_CLOCKEVENTS
1357 depends on MMU || ARM_MPU
1359 This enables support for systems with more than one CPU. If you have
1360 a system with only one CPU, say N. If you have a system with more
1361 than one CPU, say Y.
1363 If you say N here, the kernel will run on uni- and multiprocessor
1364 machines, but will use only one CPU of a multiprocessor machine. If
1365 you say Y here, the kernel will run on many, but not all,
1366 uniprocessor machines. On a uniprocessor machine, the kernel
1367 will run faster if you say N here.
1369 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1370 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1371 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1373 If you don't know what to do here, say N.
1376 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1377 depends on SMP && !XIP_KERNEL && MMU
1380 SMP kernels contain instructions which fail on non-SMP processors.
1381 Enabling this option allows the kernel to modify itself to make
1382 these instructions safe. Disabling it allows about 1K of space
1385 If you don't know what to do here, say Y.
1387 config ARM_CPU_TOPOLOGY
1388 bool "Support cpu topology definition"
1389 depends on SMP && CPU_V7
1392 Support ARM cpu topology definition. The MPIDR register defines
1393 affinity between processors which is then used to describe the cpu
1394 topology of an ARM System.
1397 bool "Multi-core scheduler support"
1398 depends on ARM_CPU_TOPOLOGY
1400 Multi-core scheduler support improves the CPU scheduler's decision
1401 making when dealing with multi-core CPU chips at a cost of slightly
1402 increased overhead in some places. If unsure say N here.
1405 bool "SMT scheduler support"
1406 depends on ARM_CPU_TOPOLOGY
1408 Improves the CPU scheduler's decision making when dealing with
1409 MultiThreading at a cost of slightly increased overhead in some
1410 places. If unsure say N here.
1415 This option enables support for the ARM system coherency unit
1417 config HAVE_ARM_ARCH_TIMER
1418 bool "Architected timer support"
1420 select ARM_ARCH_TIMER
1421 select GENERIC_CLOCKEVENTS
1423 This option enables support for the ARM architected timer
1428 select CLKSRC_OF if OF
1430 This options enables support for the ARM timer and watchdog unit
1433 bool "Multi-Cluster Power Management"
1434 depends on CPU_V7 && SMP
1436 This option provides the common power management infrastructure
1437 for (multi-)cluster based systems, such as big.LITTLE based
1441 bool "big.LITTLE support (Experimental)"
1442 depends on CPU_V7 && SMP
1445 This option enables support selections for the big.LITTLE
1446 system architecture.
1449 bool "big.LITTLE switcher support"
1450 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1451 select ARM_CPU_SUSPEND
1454 The big.LITTLE "switcher" provides the core functionality to
1455 transparently handle transition between a cluster of A15's
1456 and a cluster of A7's in a big.LITTLE system.
1458 config BL_SWITCHER_DUMMY_IF
1459 tristate "Simple big.LITTLE switcher user interface"
1460 depends on BL_SWITCHER && DEBUG_KERNEL
1462 This is a simple and dummy char dev interface to control
1463 the big.LITTLE switcher core code. It is meant for
1464 debugging purposes only.
1467 prompt "Memory split"
1471 Select the desired split between kernel and user memory.
1473 If you are not absolutely sure what you are doing, leave this
1477 bool "3G/1G user/kernel split"
1479 bool "2G/2G user/kernel split"
1481 bool "1G/3G user/kernel split"
1486 default PHYS_OFFSET if !MMU
1487 default 0x40000000 if VMSPLIT_1G
1488 default 0x80000000 if VMSPLIT_2G
1492 int "Maximum number of CPUs (2-32)"
1498 bool "Support for hot-pluggable CPUs"
1501 Say Y here to experiment with turning CPUs off and on. CPUs
1502 can be controlled through /sys/devices/system/cpu.
1505 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1508 Say Y here if you want Linux to communicate with system firmware
1509 implementing the PSCI specification for CPU-centric power
1510 management operations described in ARM document number ARM DEN
1511 0022A ("Power State Coordination Interface System Software on
1514 # The GPIO number here must be sorted by descending number. In case of
1515 # a multiplatform kernel, we just want the highest value required by the
1516 # selected platforms.
1519 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1520 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1521 default 416 if ARCH_SUNXI
1522 default 392 if ARCH_U8500
1523 default 352 if ARCH_VT8500
1524 default 264 if MACH_H4700
1527 Maximum number of GPIOs in the system.
1529 If unsure, leave the default value.
1531 source kernel/Kconfig.preempt
1535 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1536 ARCH_S5PV210 || ARCH_EXYNOS4
1537 default AT91_TIMER_HZ if ARCH_AT91
1538 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1542 depends on HZ_FIXED = 0
1543 prompt "Timer frequency"
1567 default HZ_FIXED if HZ_FIXED != 0
1568 default 100 if HZ_100
1569 default 200 if HZ_200
1570 default 250 if HZ_250
1571 default 300 if HZ_300
1572 default 500 if HZ_500
1576 def_bool HIGH_RES_TIMERS
1578 config THUMB2_KERNEL
1579 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1580 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1581 default y if CPU_THUMBONLY
1583 select ARM_ASM_UNIFIED
1586 By enabling this option, the kernel will be compiled in
1587 Thumb-2 mode. A compiler/assembler that understand the unified
1588 ARM-Thumb syntax is needed.
1592 config THUMB2_AVOID_R_ARM_THM_JUMP11
1593 bool "Work around buggy Thumb-2 short branch relocations in gas"
1594 depends on THUMB2_KERNEL && MODULES
1597 Various binutils versions can resolve Thumb-2 branches to
1598 locally-defined, preemptible global symbols as short-range "b.n"
1599 branch instructions.
1601 This is a problem, because there's no guarantee the final
1602 destination of the symbol, or any candidate locations for a
1603 trampoline, are within range of the branch. For this reason, the
1604 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1605 relocation in modules at all, and it makes little sense to add
1608 The symptom is that the kernel fails with an "unsupported
1609 relocation" error when loading some modules.
1611 Until fixed tools are available, passing
1612 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1613 code which hits this problem, at the cost of a bit of extra runtime
1614 stack usage in some cases.
1616 The problem is described in more detail at:
1617 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1619 Only Thumb-2 kernels are affected.
1621 Unless you are sure your tools don't have this problem, say Y.
1623 config ARM_ASM_UNIFIED
1627 bool "Use the ARM EABI to compile the kernel"
1629 This option allows for the kernel to be compiled using the latest
1630 ARM ABI (aka EABI). This is only useful if you are using a user
1631 space environment that is also compiled with EABI.
1633 Since there are major incompatibilities between the legacy ABI and
1634 EABI, especially with regard to structure member alignment, this
1635 option also changes the kernel syscall calling convention to
1636 disambiguate both ABIs and allow for backward compatibility support
1637 (selected with CONFIG_OABI_COMPAT).
1639 To use this you need GCC version 4.0.0 or later.
1642 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1643 depends on AEABI && !THUMB2_KERNEL
1645 This option preserves the old syscall interface along with the
1646 new (ARM EABI) one. It also provides a compatibility layer to
1647 intercept syscalls that have structure arguments which layout
1648 in memory differs between the legacy ABI and the new ARM EABI
1649 (only for non "thumb" binaries). This option adds a tiny
1650 overhead to all syscalls and produces a slightly larger kernel.
1652 The seccomp filter system will not be available when this is
1653 selected, since there is no way yet to sensibly distinguish
1654 between calling conventions during filtering.
1656 If you know you'll be using only pure EABI user space then you
1657 can say N here. If this option is not selected and you attempt
1658 to execute a legacy ABI binary then the result will be
1659 UNPREDICTABLE (in fact it can be predicted that it won't work
1660 at all). If in doubt say N.
1662 config ARCH_HAS_HOLES_MEMORYMODEL
1665 config ARCH_SPARSEMEM_ENABLE
1668 config ARCH_SPARSEMEM_DEFAULT
1669 def_bool ARCH_SPARSEMEM_ENABLE
1671 config ARCH_SELECT_MEMORY_MODEL
1672 def_bool ARCH_SPARSEMEM_ENABLE
1674 config HAVE_ARCH_PFN_VALID
1675 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1678 bool "High Memory Support"
1681 The address space of ARM processors is only 4 Gigabytes large
1682 and it has to accommodate user address space, kernel address
1683 space as well as some memory mapped IO. That means that, if you
1684 have a large amount of physical memory and/or IO, not all of the
1685 memory can be "permanently mapped" by the kernel. The physical
1686 memory that is not permanently mapped is called "high memory".
1688 Depending on the selected kernel/user memory split, minimum
1689 vmalloc space and actual amount of RAM, you may not need this
1690 option which should result in a slightly faster kernel.
1695 bool "Allocate 2nd-level pagetables from highmem"
1698 config HW_PERF_EVENTS
1699 bool "Enable hardware performance counter support for perf events"
1700 depends on PERF_EVENTS
1703 Enable hardware performance counter support for perf events. If
1704 disabled, perf events will use software events only.
1706 config SYS_SUPPORTS_HUGETLBFS
1710 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1714 config ARCH_WANT_GENERAL_HUGETLB
1719 config FORCE_MAX_ZONEORDER
1720 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1721 range 11 64 if ARCH_SHMOBILE_LEGACY
1722 default "12" if SOC_AM33XX
1723 default "9" if SA1111 || ARCH_EFM32
1726 The kernel memory allocator divides physically contiguous memory
1727 blocks into "zones", where each zone is a power of two number of
1728 pages. This option selects the largest power of two that the kernel
1729 keeps in the memory allocator. If you need to allocate very large
1730 blocks of physically contiguous memory, then you may need to
1731 increase this value.
1733 This config option is actually maximum order plus one. For example,
1734 a value of 11 means that the largest free memory block is 2^10 pages.
1736 config ALIGNMENT_TRAP
1738 depends on CPU_CP15_MMU
1739 default y if !ARCH_EBSA110
1740 select HAVE_PROC_CPU if PROC_FS
1742 ARM processors cannot fetch/store information which is not
1743 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1744 address divisible by 4. On 32-bit ARM processors, these non-aligned
1745 fetch/store instructions will be emulated in software if you say
1746 here, which has a severe performance impact. This is necessary for
1747 correct operation of some network protocols. With an IP-only
1748 configuration it is safe to say N, otherwise say Y.
1750 config UACCESS_WITH_MEMCPY
1751 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1753 default y if CPU_FEROCEON
1755 Implement faster copy_to_user and clear_user methods for CPU
1756 cores where a 8-word STM instruction give significantly higher
1757 memory write throughput than a sequence of individual 32bit stores.
1759 A possible side effect is a slight increase in scheduling latency
1760 between threads sharing the same address space if they invoke
1761 such copy operations with large buffers.
1763 However, if the CPU data cache is using a write-allocate mode,
1764 this option is unlikely to provide any performance gain.
1768 prompt "Enable seccomp to safely compute untrusted bytecode"
1770 This kernel feature is useful for number crunching applications
1771 that may need to compute untrusted bytecode during their
1772 execution. By using pipes or other transports made available to
1773 the process as file descriptors supporting the read/write
1774 syscalls, it's possible to isolate those applications in
1775 their own address space using seccomp. Once seccomp is
1776 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1777 and the task is only allowed to execute a few safe syscalls
1778 defined by each seccomp mode.
1791 bool "Xen guest support on ARM (EXPERIMENTAL)"
1792 depends on ARM && AEABI && OF
1793 depends on CPU_V7 && !CPU_V6
1794 depends on !GENERIC_ATOMIC64
1796 select ARCH_DMA_ADDR_T_64BIT
1800 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1807 bool "Flattened Device Tree support"
1810 select OF_EARLY_FLATTREE
1811 select OF_RESERVED_MEM
1813 Include support for flattened device tree machine descriptions.
1816 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1819 This is the traditional way of passing data to the kernel at boot
1820 time. If you are solely relying on the flattened device tree (or
1821 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1822 to remove ATAGS support from your kernel binary. If unsure,
1825 config DEPRECATED_PARAM_STRUCT
1826 bool "Provide old way to pass kernel parameters"
1829 This was deprecated in 2001 and announced to live on for 5 years.
1830 Some old boot loaders still use this way.
1832 # Compressed boot loader in ROM. Yes, we really want to ask about
1833 # TEXT and BSS so we preserve their values in the config files.
1834 config ZBOOT_ROM_TEXT
1835 hex "Compressed ROM boot loader base address"
1838 The physical address at which the ROM-able zImage is to be
1839 placed in the target. Platforms which normally make use of
1840 ROM-able zImage formats normally set this to a suitable
1841 value in their defconfig file.
1843 If ZBOOT_ROM is not enabled, this has no effect.
1845 config ZBOOT_ROM_BSS
1846 hex "Compressed ROM boot loader BSS address"
1849 The base address of an area of read/write memory in the target
1850 for the ROM-able zImage which must be available while the
1851 decompressor is running. It must be large enough to hold the
1852 entire decompressed kernel plus an additional 128 KiB.
1853 Platforms which normally make use of ROM-able zImage formats
1854 normally set this to a suitable value in their defconfig file.
1856 If ZBOOT_ROM is not enabled, this has no effect.
1859 bool "Compressed boot loader in ROM/flash"
1860 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1861 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1863 Say Y here if you intend to execute your compressed kernel image
1864 (zImage) directly from ROM or flash. If unsure, say N.
1867 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1868 depends on ZBOOT_ROM && ARCH_SH7372
1869 default ZBOOT_ROM_NONE
1871 Include experimental SD/MMC loading code in the ROM-able zImage.
1872 With this enabled it is possible to write the ROM-able zImage
1873 kernel image to an MMC or SD card and boot the kernel straight
1874 from the reset vector. At reset the processor Mask ROM will load
1875 the first part of the ROM-able zImage which in turn loads the
1876 rest the kernel image to RAM.
1878 config ZBOOT_ROM_NONE
1879 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1881 Do not load image from SD or MMC
1883 config ZBOOT_ROM_MMCIF
1884 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1886 Load image from MMCIF hardware block.
1888 config ZBOOT_ROM_SH_MOBILE_SDHI
1889 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1891 Load image from SDHI hardware block
1895 config ARM_APPENDED_DTB
1896 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1899 With this option, the boot code will look for a device tree binary
1900 (DTB) appended to zImage
1901 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1903 This is meant as a backward compatibility convenience for those
1904 systems with a bootloader that can't be upgraded to accommodate
1905 the documented boot protocol using a device tree.
1907 Beware that there is very little in terms of protection against
1908 this option being confused by leftover garbage in memory that might
1909 look like a DTB header after a reboot if no actual DTB is appended
1910 to zImage. Do not leave this option active in a production kernel
1911 if you don't intend to always append a DTB. Proper passing of the
1912 location into r2 of a bootloader provided DTB is always preferable
1915 config ARM_ATAG_DTB_COMPAT
1916 bool "Supplement the appended DTB with traditional ATAG information"
1917 depends on ARM_APPENDED_DTB
1919 Some old bootloaders can't be updated to a DTB capable one, yet
1920 they provide ATAGs with memory configuration, the ramdisk address,
1921 the kernel cmdline string, etc. Such information is dynamically
1922 provided by the bootloader and can't always be stored in a static
1923 DTB. To allow a device tree enabled kernel to be used with such
1924 bootloaders, this option allows zImage to extract the information
1925 from the ATAG list and store it at run time into the appended DTB.
1928 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1929 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1931 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1932 bool "Use bootloader kernel arguments if available"
1934 Uses the command-line options passed by the boot loader instead of
1935 the device tree bootargs property. If the boot loader doesn't provide
1936 any, the device tree bootargs property will be used.
1938 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1939 bool "Extend with bootloader kernel arguments"
1941 The command-line arguments provided by the boot loader will be
1942 appended to the the device tree bootargs property.
1947 string "Default kernel command string"
1950 On some architectures (EBSA110 and CATS), there is currently no way
1951 for the boot loader to pass arguments to the kernel. For these
1952 architectures, you should supply some command-line options at build
1953 time by entering them here. As a minimum, you should specify the
1954 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1957 prompt "Kernel command line type" if CMDLINE != ""
1958 default CMDLINE_FROM_BOOTLOADER
1961 config CMDLINE_FROM_BOOTLOADER
1962 bool "Use bootloader kernel arguments if available"
1964 Uses the command-line options passed by the boot loader. If
1965 the boot loader doesn't provide any, the default kernel command
1966 string provided in CMDLINE will be used.
1968 config CMDLINE_EXTEND
1969 bool "Extend bootloader kernel arguments"
1971 The command-line arguments provided by the boot loader will be
1972 appended to the default kernel command string.
1974 config CMDLINE_FORCE
1975 bool "Always use the default kernel command string"
1977 Always use the default kernel command string, even if the boot
1978 loader passes other arguments to the kernel.
1979 This is useful if you cannot or don't want to change the
1980 command-line options your boot loader passes to the kernel.
1984 bool "Kernel Execute-In-Place from ROM"
1985 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1987 Execute-In-Place allows the kernel to run from non-volatile storage
1988 directly addressable by the CPU, such as NOR flash. This saves RAM
1989 space since the text section of the kernel is not loaded from flash
1990 to RAM. Read-write sections, such as the data section and stack,
1991 are still copied to RAM. The XIP kernel is not compressed since
1992 it has to run directly from flash, so it will take more space to
1993 store it. The flash address used to link the kernel object files,
1994 and for storing it, is configuration dependent. Therefore, if you
1995 say Y here, you must know the proper physical address where to
1996 store the kernel image depending on your own flash memory usage.
1998 Also note that the make target becomes "make xipImage" rather than
1999 "make zImage" or "make Image". The final kernel binary to put in
2000 ROM memory will be arch/arm/boot/xipImage.
2004 config XIP_PHYS_ADDR
2005 hex "XIP Kernel Physical Location"
2006 depends on XIP_KERNEL
2007 default "0x00080000"
2009 This is the physical address in your flash memory the kernel will
2010 be linked for and stored to. This address is dependent on your
2014 bool "Kexec system call (EXPERIMENTAL)"
2015 depends on (!SMP || PM_SLEEP_SMP)
2017 kexec is a system call that implements the ability to shutdown your
2018 current kernel, and to start another kernel. It is like a reboot
2019 but it is independent of the system firmware. And like a reboot
2020 you can start any kernel with it, not just Linux.
2022 It is an ongoing process to be certain the hardware in a machine
2023 is properly shutdown, so do not be surprised if this code does not
2024 initially work for you.
2027 bool "Export atags in procfs"
2028 depends on ATAGS && KEXEC
2031 Should the atags used to boot the kernel be exported in an "atags"
2032 file in procfs. Useful with kexec.
2035 bool "Build kdump crash kernel (EXPERIMENTAL)"
2037 Generate crash dump after being started by kexec. This should
2038 be normally only set in special crash dump kernels which are
2039 loaded in the main kernel with kexec-tools into a specially
2040 reserved region and then later executed after a crash by
2041 kdump/kexec. The crash dump kernel must be compiled to a
2042 memory address not used by the main kernel
2044 For more details see Documentation/kdump/kdump.txt
2046 config AUTO_ZRELADDR
2047 bool "Auto calculation of the decompressed kernel image address"
2049 ZRELADDR is the physical address where the decompressed kernel
2050 image will be placed. If AUTO_ZRELADDR is selected, the address
2051 will be determined at run-time by masking the current IP with
2052 0xf8000000. This assumes the zImage being placed in the first 128MB
2053 from start of memory.
2057 menu "CPU Power Management"
2059 source "drivers/cpufreq/Kconfig"
2061 source "drivers/cpuidle/Kconfig"
2065 menu "Floating point emulation"
2067 comment "At least one emulation must be selected"
2070 bool "NWFPE math emulation"
2071 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2073 Say Y to include the NWFPE floating point emulator in the kernel.
2074 This is necessary to run most binaries. Linux does not currently
2075 support floating point hardware so you need to say Y here even if
2076 your machine has an FPA or floating point co-processor podule.
2078 You may say N here if you are going to load the Acorn FPEmulator
2079 early in the bootup.
2082 bool "Support extended precision"
2083 depends on FPE_NWFPE
2085 Say Y to include 80-bit support in the kernel floating-point
2086 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2087 Note that gcc does not generate 80-bit operations by default,
2088 so in most cases this option only enlarges the size of the
2089 floating point emulator without any good reason.
2091 You almost surely want to say N here.
2094 bool "FastFPE math emulation (EXPERIMENTAL)"
2095 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2097 Say Y here to include the FAST floating point emulator in the kernel.
2098 This is an experimental much faster emulator which now also has full
2099 precision for the mantissa. It does not support any exceptions.
2100 It is very simple, and approximately 3-6 times faster than NWFPE.
2102 It should be sufficient for most programs. It may be not suitable
2103 for scientific calculations, but you have to check this for yourself.
2104 If you do not feel you need a faster FP emulation you should better
2108 bool "VFP-format floating point maths"
2109 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2111 Say Y to include VFP support code in the kernel. This is needed
2112 if your hardware includes a VFP unit.
2114 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2115 release notes and additional status information.
2117 Say N if your target does not have VFP hardware.
2125 bool "Advanced SIMD (NEON) Extension support"
2126 depends on VFPv3 && CPU_V7
2128 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2131 config KERNEL_MODE_NEON
2132 bool "Support for NEON in kernel mode"
2133 depends on NEON && AEABI
2135 Say Y to include support for NEON in kernel mode.
2139 menu "Userspace binary formats"
2141 source "fs/Kconfig.binfmt"
2144 tristate "RISC OS personality"
2147 Say Y here to include the kernel code necessary if you want to run
2148 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2149 experimental; if this sounds frightening, say N and sleep in peace.
2150 You can also say M here to compile this support as a module (which
2151 will be called arthur).
2155 menu "Power management options"
2157 source "kernel/power/Kconfig"
2159 config ARCH_SUSPEND_POSSIBLE
2160 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2161 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2164 config ARM_CPU_SUSPEND
2167 config ARCH_HIBERNATION_POSSIBLE
2170 default y if ARCH_SUSPEND_POSSIBLE
2174 source "net/Kconfig"
2176 source "drivers/Kconfig"
2180 source "arch/arm/Kconfig.debug"
2182 source "security/Kconfig"
2184 source "crypto/Kconfig"
2186 source "lib/Kconfig"
2188 source "arch/arm/kvm/Kconfig"