4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_XCHGADD_ALGORITHM
172 config ARCH_HAS_ILOG2_U32
175 config ARCH_HAS_ILOG2_U64
178 config ARCH_HAS_BANDGAP
181 config GENERIC_HWEIGHT
185 config GENERIC_CALIBRATE_DELAY
189 config ARCH_MAY_HAVE_PC_FDC
195 config NEED_DMA_MAP_STATE
198 config ARCH_SUPPORTS_UPROBES
201 config ARCH_HAS_DMA_SET_COHERENT_MASK
204 config GENERIC_ISA_DMA
210 config NEED_RET_TO_USER
218 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
219 default DRAM_BASE if REMAP_VECTORS_TO_RAM
222 The base address of exception vectors. This must be two pages
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
228 depends on !XIP_KERNEL && MMU
229 depends on !ARCH_REALVIEW || !SPARSEMEM
231 Patch phys-to-virt and virt-to-phys translation functions at
232 boot and module load time according to the position of the
233 kernel in system memory.
235 This can only be used with non-XIP MMU kernels where the base
236 of physical memory is at a 16MB boundary.
238 Only disable this option if you know that you do not require
239 this feature (eg, building a kernel for a single machine) and
240 you need to shrink the kernel to the minimal size.
242 config NEED_MACH_GPIO_H
245 Select this when mach/gpio.h is required to provide special
246 definitions for this platform. The need for mach/gpio.h should
247 be avoided when possible.
249 config NEED_MACH_IO_H
252 Select this when mach/io.h is required to provide special
253 definitions for this platform. The need for mach/io.h should
254 be avoided when possible.
256 config NEED_MACH_MEMORY_H
259 Select this when mach/memory.h is required to provide special
260 definitions for this platform. The need for mach/memory.h should
261 be avoided when possible.
264 hex "Physical address of main memory" if MMU
265 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
266 default DRAM_BASE if !MMU
268 Please provide the physical address corresponding to the
269 location of main memory in your system.
275 source "init/Kconfig"
277 source "kernel/Kconfig.freezer"
282 bool "MMU-based Paged Memory Management Support"
285 Select if you want MMU-based virtualised addressing space
286 support by paged memory management. If unsure, say 'Y'.
289 # The "ARM system type" choice list is ordered alphabetically by option
290 # text. Please add new entries in the option alphabetic order.
293 prompt "ARM system type"
294 default ARCH_VERSATILE if !MMU
295 default ARCH_MULTIPLATFORM if MMU
297 config ARCH_MULTIPLATFORM
298 bool "Allow multiple platforms to be selected"
300 select ARCH_WANT_OPTIONAL_GPIOLIB
301 select ARM_HAS_SG_CHAIN
302 select ARM_PATCH_PHYS_VIRT
306 select GENERIC_CLOCKEVENTS
307 select MIGHT_HAVE_PCI
308 select MULTI_IRQ_HANDLER
312 config ARCH_INTEGRATOR
313 bool "ARM Ltd. Integrator family"
315 select ARM_PATCH_PHYS_VIRT
318 select COMMON_CLK_VERSATILE
319 select GENERIC_CLOCKEVENTS
322 select MULTI_IRQ_HANDLER
323 select PLAT_VERSATILE
326 select VERSATILE_FPGA_IRQ
328 Support for ARM's Integrator platform.
331 bool "ARM Ltd. RealView family"
332 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_TIMER_SP804
336 select COMMON_CLK_VERSATILE
337 select GENERIC_CLOCKEVENTS
338 select GPIO_PL061 if GPIOLIB
340 select NEED_MACH_MEMORY_H
341 select PLAT_VERSATILE
342 select PLAT_VERSATILE_CLCD
344 This enables support for ARM Ltd RealView boards.
346 config ARCH_VERSATILE
347 bool "ARM Ltd. Versatile family"
348 select ARCH_WANT_OPTIONAL_GPIOLIB
350 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
354 select HAVE_MACH_CLKDEV
356 select PLAT_VERSATILE
357 select PLAT_VERSATILE_CLCD
358 select PLAT_VERSATILE_CLOCK
359 select VERSATILE_FPGA_IRQ
361 This enables support for ARM Ltd Versatile board.
365 select ARCH_REQUIRE_GPIOLIB
368 select NEED_MACH_IO_H if PCCARD
370 select PINCTRL_AT91 if USE_OF
372 This enables support for systems based on Atmel
373 AT91RM9200 and AT91SAM9* processors.
376 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
377 select ARCH_REQUIRE_GPIOLIB
382 select GENERIC_CLOCKEVENTS
385 Support for Cirrus Logic 711x/721x/731x based boards.
388 bool "Cortina Systems Gemini"
389 select ARCH_REQUIRE_GPIOLIB
392 select GENERIC_CLOCKEVENTS
394 Support for the Cortina Systems Gemini family SoCs
398 select ARCH_USES_GETTIMEOFFSET
401 select NEED_MACH_IO_H
402 select NEED_MACH_MEMORY_H
405 This is an evaluation board for the StrongARM processor available
406 from Digital. It has limited hardware on-board, including an
407 Ethernet interface, two PCMCIA sockets, two serial ports and a
411 bool "Energy Micro efm32"
413 select ARCH_REQUIRE_GPIOLIB
419 select GENERIC_CLOCKEVENTS
425 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
430 select ARCH_HAS_HOLES_MEMORYMODEL
431 select ARCH_REQUIRE_GPIOLIB
432 select ARCH_USES_GETTIMEOFFSET
437 select NEED_MACH_MEMORY_H
439 This enables support for the Cirrus EP93xx series of CPUs.
441 config ARCH_FOOTBRIDGE
445 select GENERIC_CLOCKEVENTS
447 select NEED_MACH_IO_H if !MMU
448 select NEED_MACH_MEMORY_H
450 Support for systems based on the DC21285 companion chip
451 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
454 bool "Hilscher NetX based"
458 select GENERIC_CLOCKEVENTS
460 This enables support for systems based on the Hilscher NetX Soc
466 select NEED_MACH_MEMORY_H
467 select NEED_RET_TO_USER
473 Support for Intel's IOP13XX (XScale) family of processors.
478 select ARCH_REQUIRE_GPIOLIB
481 select NEED_RET_TO_USER
485 Support for Intel's 80219 and IOP32X (XScale) family of
491 select ARCH_REQUIRE_GPIOLIB
494 select NEED_RET_TO_USER
498 Support for Intel's IOP33X (XScale) family of processors.
503 select ARCH_HAS_DMA_SET_COHERENT_MASK
504 select ARCH_REQUIRE_GPIOLIB
505 select ARCH_SUPPORTS_BIG_ENDIAN
508 select DMABOUNCE if PCI
509 select GENERIC_CLOCKEVENTS
510 select MIGHT_HAVE_PCI
511 select NEED_MACH_IO_H
512 select USB_EHCI_BIG_ENDIAN_DESC
513 select USB_EHCI_BIG_ENDIAN_MMIO
515 Support for Intel's IXP4XX (XScale) family of processors.
519 select ARCH_REQUIRE_GPIOLIB
521 select GENERIC_CLOCKEVENTS
522 select MIGHT_HAVE_PCI
526 select PLAT_ORION_LEGACY
528 Support for the Marvell Dove SoC 88AP510
531 bool "Marvell Kirkwood"
532 select ARCH_REQUIRE_GPIOLIB
534 select GENERIC_CLOCKEVENTS
539 select PINCTRL_KIRKWOOD
540 select PLAT_ORION_LEGACY
542 Support for the following Marvell Kirkwood series SoCs:
543 88F6180, 88F6192 and 88F6281.
546 bool "Marvell MV78xx0"
547 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_CLOCKEVENTS
552 select PLAT_ORION_LEGACY
554 Support for the following Marvell MV78xx0 series SoCs:
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
565 select PLAT_ORION_LEGACY
567 Support for the following Marvell Orion 5x series SoCs:
568 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
569 Orion-2 (5281), Orion-1-90 (6183).
572 bool "Marvell PXA168/910/MMP2"
574 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_ALLOCATOR
577 select GENERIC_CLOCKEVENTS
580 select MULTI_IRQ_HANDLER
585 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
588 bool "Micrel/Kendin KS8695"
589 select ARCH_REQUIRE_GPIOLIB
592 select GENERIC_CLOCKEVENTS
593 select NEED_MACH_MEMORY_H
595 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
596 System-on-Chip devices.
599 bool "Nuvoton W90X900 CPU"
600 select ARCH_REQUIRE_GPIOLIB
604 select GENERIC_CLOCKEVENTS
606 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
607 At present, the w90x900 has been renamed nuc900, regarding
608 the ARM series product line, you can login the following
609 link address to know more.
611 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
612 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
616 select ARCH_REQUIRE_GPIOLIB
621 select GENERIC_CLOCKEVENTS
625 Support for the NXP LPC32XX family of processors
628 bool "PXA2xx/PXA3xx-based"
631 select ARCH_REQUIRE_GPIOLIB
632 select ARM_CPU_SUSPEND if PM
636 select GENERIC_CLOCKEVENTS
639 select MULTI_IRQ_HANDLER
643 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
646 bool "Qualcomm MSM (non-multiplatform)"
647 select ARCH_REQUIRE_GPIOLIB
649 select GENERIC_CLOCKEVENTS
651 Support for Qualcomm MSM/QSD based systems. This runs on the
652 apps processor of the MSM/QSD and depends on a shared memory
653 interface to the modem processor which runs the baseband
654 stack and controls some vital subsystems
655 (clock and power control, etc).
657 config ARCH_SHMOBILE_LEGACY
658 bool "Renesas ARM SoCs (non-multiplatform)"
660 select ARM_PATCH_PHYS_VIRT
662 select GENERIC_CLOCKEVENTS
663 select HAVE_ARM_SCU if SMP
664 select HAVE_ARM_TWD if SMP
665 select HAVE_MACH_CLKDEV
667 select MIGHT_HAVE_CACHE_L2X0
668 select MULTI_IRQ_HANDLER
671 select PM_GENERIC_DOMAINS if PM
674 Support for Renesas ARM SoC platforms using a non-multiplatform
675 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
681 select ARCH_MAY_HAVE_PC_FDC
682 select ARCH_SPARSEMEM_ENABLE
683 select ARCH_USES_GETTIMEOFFSET
687 select HAVE_PATA_PLATFORM
689 select NEED_MACH_IO_H
690 select NEED_MACH_MEMORY_H
694 On the Acorn Risc-PC, Linux can support the internal IDE disk and
695 CD-ROM interface, serial and parallel port, and the floppy drive.
700 select ARCH_REQUIRE_GPIOLIB
701 select ARCH_SPARSEMEM_ENABLE
706 select GENERIC_CLOCKEVENTS
709 select NEED_MACH_MEMORY_H
712 Support for StrongARM 11x0 based boards.
715 bool "Samsung S3C24XX SoCs"
716 select ARCH_REQUIRE_GPIOLIB
719 select CLKSRC_SAMSUNG_PWM
720 select GENERIC_CLOCKEVENTS
722 select HAVE_S3C2410_I2C if I2C
723 select HAVE_S3C2410_WATCHDOG if WATCHDOG
724 select HAVE_S3C_RTC if RTC_CLASS
725 select MULTI_IRQ_HANDLER
726 select NEED_MACH_IO_H
729 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
730 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
731 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
732 Samsung SMDK2410 development board (and derivatives).
735 bool "Samsung S3C64XX"
736 select ARCH_REQUIRE_GPIOLIB
741 select CLKSRC_SAMSUNG_PWM
742 select COMMON_CLK_SAMSUNG
744 select GENERIC_CLOCKEVENTS
746 select HAVE_S3C2410_I2C if I2C
747 select HAVE_S3C2410_WATCHDOG if WATCHDOG
751 select PM_GENERIC_DOMAINS if PM
753 select S3C_GPIO_TRACK
755 select SAMSUNG_WAKEMASK
756 select SAMSUNG_WDT_RESET
758 Samsung S3C64XX series based systems
761 bool "Samsung S5PV210/S5PC110"
762 select ARCH_HAS_HOLES_MEMORYMODEL
763 select ARCH_SPARSEMEM_ENABLE
766 select CLKSRC_SAMSUNG_PWM
768 select GENERIC_CLOCKEVENTS
770 select HAVE_S3C2410_I2C if I2C
771 select HAVE_S3C2410_WATCHDOG if WATCHDOG
772 select HAVE_S3C_RTC if RTC_CLASS
773 select NEED_MACH_GPIO_H
774 select NEED_MACH_MEMORY_H
777 Samsung S5PV210/S5PC110 series based systems
781 select ARCH_HAS_HOLES_MEMORYMODEL
782 select ARCH_REQUIRE_GPIOLIB
784 select GENERIC_ALLOCATOR
785 select GENERIC_CLOCKEVENTS
786 select GENERIC_IRQ_CHIP
792 Support for TI's DaVinci platform.
797 select ARCH_HAS_HOLES_MEMORYMODEL
799 select ARCH_REQUIRE_GPIOLIB
802 select GENERIC_CLOCKEVENTS
803 select GENERIC_IRQ_CHIP
806 select NEED_MACH_IO_H if PCCARD
807 select NEED_MACH_MEMORY_H
809 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
813 menu "Multiple platform selection"
814 depends on ARCH_MULTIPLATFORM
816 comment "CPU Core family selection"
819 bool "ARMv4 based platforms (FA526)"
820 depends on !ARCH_MULTI_V6_V7
821 select ARCH_MULTI_V4_V5
824 config ARCH_MULTI_V4T
825 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
826 depends on !ARCH_MULTI_V6_V7
827 select ARCH_MULTI_V4_V5
828 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
829 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
830 CPU_ARM925T || CPU_ARM940T)
833 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
834 depends on !ARCH_MULTI_V6_V7
835 select ARCH_MULTI_V4_V5
836 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
837 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
838 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
840 config ARCH_MULTI_V4_V5
844 bool "ARMv6 based platforms (ARM11)"
845 select ARCH_MULTI_V6_V7
849 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
851 select ARCH_MULTI_V6_V7
855 config ARCH_MULTI_V6_V7
857 select MIGHT_HAVE_CACHE_L2X0
859 config ARCH_MULTI_CPU_AUTO
860 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
866 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
870 select HAVE_ARM_ARCH_TIMER
873 # This is sorted alphabetically by mach-* pathname. However, plat-*
874 # Kconfigs may be included either alphabetically (according to the
875 # plat- suffix) or along side the corresponding mach-* source.
877 source "arch/arm/mach-mvebu/Kconfig"
879 source "arch/arm/mach-at91/Kconfig"
881 source "arch/arm/mach-axxia/Kconfig"
883 source "arch/arm/mach-bcm/Kconfig"
885 source "arch/arm/mach-berlin/Kconfig"
887 source "arch/arm/mach-clps711x/Kconfig"
889 source "arch/arm/mach-cns3xxx/Kconfig"
891 source "arch/arm/mach-davinci/Kconfig"
893 source "arch/arm/mach-dove/Kconfig"
895 source "arch/arm/mach-ep93xx/Kconfig"
897 source "arch/arm/mach-footbridge/Kconfig"
899 source "arch/arm/mach-gemini/Kconfig"
901 source "arch/arm/mach-highbank/Kconfig"
903 source "arch/arm/mach-hisi/Kconfig"
905 source "arch/arm/mach-integrator/Kconfig"
907 source "arch/arm/mach-iop32x/Kconfig"
909 source "arch/arm/mach-iop33x/Kconfig"
911 source "arch/arm/mach-iop13xx/Kconfig"
913 source "arch/arm/mach-ixp4xx/Kconfig"
915 source "arch/arm/mach-keystone/Kconfig"
917 source "arch/arm/mach-kirkwood/Kconfig"
919 source "arch/arm/mach-ks8695/Kconfig"
921 source "arch/arm/mach-msm/Kconfig"
923 source "arch/arm/mach-moxart/Kconfig"
925 source "arch/arm/mach-mv78xx0/Kconfig"
927 source "arch/arm/mach-imx/Kconfig"
929 source "arch/arm/mach-mxs/Kconfig"
931 source "arch/arm/mach-netx/Kconfig"
933 source "arch/arm/mach-nomadik/Kconfig"
935 source "arch/arm/mach-nspire/Kconfig"
937 source "arch/arm/plat-omap/Kconfig"
939 source "arch/arm/mach-omap1/Kconfig"
941 source "arch/arm/mach-omap2/Kconfig"
943 source "arch/arm/mach-orion5x/Kconfig"
945 source "arch/arm/mach-picoxcell/Kconfig"
947 source "arch/arm/mach-pxa/Kconfig"
948 source "arch/arm/plat-pxa/Kconfig"
950 source "arch/arm/mach-mmp/Kconfig"
952 source "arch/arm/mach-qcom/Kconfig"
954 source "arch/arm/mach-realview/Kconfig"
956 source "arch/arm/mach-rockchip/Kconfig"
958 source "arch/arm/mach-sa1100/Kconfig"
960 source "arch/arm/mach-socfpga/Kconfig"
962 source "arch/arm/mach-spear/Kconfig"
964 source "arch/arm/mach-sti/Kconfig"
966 source "arch/arm/mach-s3c24xx/Kconfig"
968 source "arch/arm/mach-s3c64xx/Kconfig"
970 source "arch/arm/mach-s5pv210/Kconfig"
972 source "arch/arm/mach-exynos/Kconfig"
973 source "arch/arm/plat-samsung/Kconfig"
975 source "arch/arm/mach-shmobile/Kconfig"
977 source "arch/arm/mach-sunxi/Kconfig"
979 source "arch/arm/mach-prima2/Kconfig"
981 source "arch/arm/mach-tegra/Kconfig"
983 source "arch/arm/mach-u300/Kconfig"
985 source "arch/arm/mach-ux500/Kconfig"
987 source "arch/arm/mach-versatile/Kconfig"
989 source "arch/arm/mach-vexpress/Kconfig"
990 source "arch/arm/plat-versatile/Kconfig"
992 source "arch/arm/mach-vt8500/Kconfig"
994 source "arch/arm/mach-w90x900/Kconfig"
996 source "arch/arm/mach-zynq/Kconfig"
998 # Definitions to make life easier
1004 select GENERIC_CLOCKEVENTS
1010 select GENERIC_IRQ_CHIP
1013 config PLAT_ORION_LEGACY
1020 config PLAT_VERSATILE
1023 config ARM_TIMER_SP804
1026 select CLKSRC_OF if OF
1028 source "arch/arm/firmware/Kconfig"
1030 source arch/arm/mm/Kconfig
1033 bool "Enable iWMMXt support"
1034 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1035 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1037 Enable support for iWMMXt context switching at run time if
1038 running on a CPU that supports it.
1040 config MULTI_IRQ_HANDLER
1043 Allow each machine to specify it's own IRQ handler at run time.
1046 source "arch/arm/Kconfig-nommu"
1049 config PJ4B_ERRATA_4742
1050 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1051 depends on CPU_PJ4B && MACH_ARMADA_370
1054 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1055 Event (WFE) IDLE states, a specific timing sensitivity exists between
1056 the retiring WFI/WFE instructions and the newly issued subsequent
1057 instructions. This sensitivity can result in a CPU hang scenario.
1059 The software must insert either a Data Synchronization Barrier (DSB)
1060 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1063 config ARM_ERRATA_326103
1064 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1067 Executing a SWP instruction to read-only memory does not set bit 11
1068 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1069 treat the access as a read, preventing a COW from occurring and
1070 causing the faulting task to livelock.
1072 config ARM_ERRATA_411920
1073 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1074 depends on CPU_V6 || CPU_V6K
1076 Invalidation of the Instruction Cache operation can
1077 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1078 It does not affect the MPCore. This option enables the ARM Ltd.
1079 recommended workaround.
1081 config ARM_ERRATA_430973
1082 bool "ARM errata: Stale prediction on replaced interworking branch"
1085 This option enables the workaround for the 430973 Cortex-A8
1086 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1087 interworking branch is replaced with another code sequence at the
1088 same virtual address, whether due to self-modifying code or virtual
1089 to physical address re-mapping, Cortex-A8 does not recover from the
1090 stale interworking branch prediction. This results in Cortex-A8
1091 executing the new code sequence in the incorrect ARM or Thumb state.
1092 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1093 and also flushes the branch target cache at every context switch.
1094 Note that setting specific bits in the ACTLR register may not be
1095 available in non-secure mode.
1097 config ARM_ERRATA_458693
1098 bool "ARM errata: Processor deadlock when a false hazard is created"
1100 depends on !ARCH_MULTIPLATFORM
1102 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1103 erratum. For very specific sequences of memory operations, it is
1104 possible for a hazard condition intended for a cache line to instead
1105 be incorrectly associated with a different cache line. This false
1106 hazard might then cause a processor deadlock. The workaround enables
1107 the L1 caching of the NEON accesses and disables the PLD instruction
1108 in the ACTLR register. Note that setting specific bits in the ACTLR
1109 register may not be available in non-secure mode.
1111 config ARM_ERRATA_460075
1112 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1114 depends on !ARCH_MULTIPLATFORM
1116 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1117 erratum. Any asynchronous access to the L2 cache may encounter a
1118 situation in which recent store transactions to the L2 cache are lost
1119 and overwritten with stale memory contents from external memory. The
1120 workaround disables the write-allocate mode for the L2 cache via the
1121 ACTLR register. Note that setting specific bits in the ACTLR register
1122 may not be available in non-secure mode.
1124 config ARM_ERRATA_742230
1125 bool "ARM errata: DMB operation may be faulty"
1126 depends on CPU_V7 && SMP
1127 depends on !ARCH_MULTIPLATFORM
1129 This option enables the workaround for the 742230 Cortex-A9
1130 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1131 between two write operations may not ensure the correct visibility
1132 ordering of the two writes. This workaround sets a specific bit in
1133 the diagnostic register of the Cortex-A9 which causes the DMB
1134 instruction to behave as a DSB, ensuring the correct behaviour of
1137 config ARM_ERRATA_742231
1138 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1139 depends on CPU_V7 && SMP
1140 depends on !ARCH_MULTIPLATFORM
1142 This option enables the workaround for the 742231 Cortex-A9
1143 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1144 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1145 accessing some data located in the same cache line, may get corrupted
1146 data due to bad handling of the address hazard when the line gets
1147 replaced from one of the CPUs at the same time as another CPU is
1148 accessing it. This workaround sets specific bits in the diagnostic
1149 register of the Cortex-A9 which reduces the linefill issuing
1150 capabilities of the processor.
1152 config ARM_ERRATA_643719
1153 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1154 depends on CPU_V7 && SMP
1156 This option enables the workaround for the 643719 Cortex-A9 (prior to
1157 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1158 register returns zero when it should return one. The workaround
1159 corrects this value, ensuring cache maintenance operations which use
1160 it behave as intended and avoiding data corruption.
1162 config ARM_ERRATA_720789
1163 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1166 This option enables the workaround for the 720789 Cortex-A9 (prior to
1167 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1168 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1169 As a consequence of this erratum, some TLB entries which should be
1170 invalidated are not, resulting in an incoherency in the system page
1171 tables. The workaround changes the TLB flushing routines to invalidate
1172 entries regardless of the ASID.
1174 config ARM_ERRATA_743622
1175 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1177 depends on !ARCH_MULTIPLATFORM
1179 This option enables the workaround for the 743622 Cortex-A9
1180 (r2p*) erratum. Under very rare conditions, a faulty
1181 optimisation in the Cortex-A9 Store Buffer may lead to data
1182 corruption. This workaround sets a specific bit in the diagnostic
1183 register of the Cortex-A9 which disables the Store Buffer
1184 optimisation, preventing the defect from occurring. This has no
1185 visible impact on the overall performance or power consumption of the
1188 config ARM_ERRATA_751472
1189 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1191 depends on !ARCH_MULTIPLATFORM
1193 This option enables the workaround for the 751472 Cortex-A9 (prior
1194 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1195 completion of a following broadcasted operation if the second
1196 operation is received by a CPU before the ICIALLUIS has completed,
1197 potentially leading to corrupted entries in the cache or TLB.
1199 config ARM_ERRATA_754322
1200 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1203 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1204 r3p*) erratum. A speculative memory access may cause a page table walk
1205 which starts prior to an ASID switch but completes afterwards. This
1206 can populate the micro-TLB with a stale entry which may be hit with
1207 the new ASID. This workaround places two dsb instructions in the mm
1208 switching code so that no page table walks can cross the ASID switch.
1210 config ARM_ERRATA_754327
1211 bool "ARM errata: no automatic Store Buffer drain"
1212 depends on CPU_V7 && SMP
1214 This option enables the workaround for the 754327 Cortex-A9 (prior to
1215 r2p0) erratum. The Store Buffer does not have any automatic draining
1216 mechanism and therefore a livelock may occur if an external agent
1217 continuously polls a memory location waiting to observe an update.
1218 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1219 written polling loops from denying visibility of updates to memory.
1221 config ARM_ERRATA_364296
1222 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1225 This options enables the workaround for the 364296 ARM1136
1226 r0p2 erratum (possible cache data corruption with
1227 hit-under-miss enabled). It sets the undocumented bit 31 in
1228 the auxiliary control register and the FI bit in the control
1229 register, thus disabling hit-under-miss without putting the
1230 processor into full low interrupt latency mode. ARM11MPCore
1233 config ARM_ERRATA_764369
1234 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1235 depends on CPU_V7 && SMP
1237 This option enables the workaround for erratum 764369
1238 affecting Cortex-A9 MPCore with two or more processors (all
1239 current revisions). Under certain timing circumstances, a data
1240 cache line maintenance operation by MVA targeting an Inner
1241 Shareable memory region may fail to proceed up to either the
1242 Point of Coherency or to the Point of Unification of the
1243 system. This workaround adds a DSB instruction before the
1244 relevant cache maintenance functions and sets a specific bit
1245 in the diagnostic control register of the SCU.
1247 config ARM_ERRATA_775420
1248 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1251 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1252 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1253 operation aborts with MMU exception, it might cause the processor
1254 to deadlock. This workaround puts DSB before executing ISB if
1255 an abort may occur on cache maintenance.
1257 config ARM_ERRATA_798181
1258 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1259 depends on CPU_V7 && SMP
1261 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1262 adequately shooting down all use of the old entries. This
1263 option enables the Linux kernel workaround for this erratum
1264 which sends an IPI to the CPUs that are running the same ASID
1265 as the one being invalidated.
1267 config ARM_ERRATA_773022
1268 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1271 This option enables the workaround for the 773022 Cortex-A15
1272 (up to r0p4) erratum. In certain rare sequences of code, the
1273 loop buffer may deliver incorrect instructions. This
1274 workaround disables the loop buffer to avoid the erratum.
1278 source "arch/arm/common/Kconfig"
1288 Find out whether you have ISA slots on your motherboard. ISA is the
1289 name of a bus system, i.e. the way the CPU talks to the other stuff
1290 inside your box. Other bus systems are PCI, EISA, MicroChannel
1291 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1292 newer boards don't support it. If you have ISA, say Y, otherwise N.
1294 # Select ISA DMA controller support
1299 # Select ISA DMA interface
1304 bool "PCI support" if MIGHT_HAVE_PCI
1306 Find out whether you have a PCI motherboard. PCI is the name of a
1307 bus system, i.e. the way the CPU talks to the other stuff inside
1308 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1309 VESA. If you have PCI, say Y, otherwise N.
1315 config PCI_NANOENGINE
1316 bool "BSE nanoEngine PCI support"
1317 depends on SA1100_NANOENGINE
1319 Enable PCI on the BSE nanoEngine board.
1324 config PCI_HOST_ITE8152
1326 depends on PCI && MACH_ARMCORE
1330 source "drivers/pci/Kconfig"
1331 source "drivers/pci/pcie/Kconfig"
1333 source "drivers/pcmcia/Kconfig"
1337 menu "Kernel Features"
1342 This option should be selected by machines which have an SMP-
1345 The only effect of this option is to make the SMP-related
1346 options available to the user for configuration.
1349 bool "Symmetric Multi-Processing"
1350 depends on CPU_V6K || CPU_V7
1351 depends on GENERIC_CLOCKEVENTS
1353 depends on MMU || ARM_MPU
1355 This enables support for systems with more than one CPU. If you have
1356 a system with only one CPU, say N. If you have a system with more
1357 than one CPU, say Y.
1359 If you say N here, the kernel will run on uni- and multiprocessor
1360 machines, but will use only one CPU of a multiprocessor machine. If
1361 you say Y here, the kernel will run on many, but not all,
1362 uniprocessor machines. On a uniprocessor machine, the kernel
1363 will run faster if you say N here.
1365 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1366 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1367 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1369 If you don't know what to do here, say N.
1372 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1373 depends on SMP && !XIP_KERNEL && MMU
1376 SMP kernels contain instructions which fail on non-SMP processors.
1377 Enabling this option allows the kernel to modify itself to make
1378 these instructions safe. Disabling it allows about 1K of space
1381 If you don't know what to do here, say Y.
1383 config ARM_CPU_TOPOLOGY
1384 bool "Support cpu topology definition"
1385 depends on SMP && CPU_V7
1388 Support ARM cpu topology definition. The MPIDR register defines
1389 affinity between processors which is then used to describe the cpu
1390 topology of an ARM System.
1393 bool "Multi-core scheduler support"
1394 depends on ARM_CPU_TOPOLOGY
1396 Multi-core scheduler support improves the CPU scheduler's decision
1397 making when dealing with multi-core CPU chips at a cost of slightly
1398 increased overhead in some places. If unsure say N here.
1401 bool "SMT scheduler support"
1402 depends on ARM_CPU_TOPOLOGY
1404 Improves the CPU scheduler's decision making when dealing with
1405 MultiThreading at a cost of slightly increased overhead in some
1406 places. If unsure say N here.
1411 This option enables support for the ARM system coherency unit
1413 config HAVE_ARM_ARCH_TIMER
1414 bool "Architected timer support"
1416 select ARM_ARCH_TIMER
1417 select GENERIC_CLOCKEVENTS
1419 This option enables support for the ARM architected timer
1424 select CLKSRC_OF if OF
1426 This options enables support for the ARM timer and watchdog unit
1429 bool "Multi-Cluster Power Management"
1430 depends on CPU_V7 && SMP
1432 This option provides the common power management infrastructure
1433 for (multi-)cluster based systems, such as big.LITTLE based
1437 bool "big.LITTLE support (Experimental)"
1438 depends on CPU_V7 && SMP
1441 This option enables support selections for the big.LITTLE
1442 system architecture.
1445 bool "big.LITTLE switcher support"
1446 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1447 select ARM_CPU_SUSPEND
1450 The big.LITTLE "switcher" provides the core functionality to
1451 transparently handle transition between a cluster of A15's
1452 and a cluster of A7's in a big.LITTLE system.
1454 config BL_SWITCHER_DUMMY_IF
1455 tristate "Simple big.LITTLE switcher user interface"
1456 depends on BL_SWITCHER && DEBUG_KERNEL
1458 This is a simple and dummy char dev interface to control
1459 the big.LITTLE switcher core code. It is meant for
1460 debugging purposes only.
1463 prompt "Memory split"
1467 Select the desired split between kernel and user memory.
1469 If you are not absolutely sure what you are doing, leave this
1473 bool "3G/1G user/kernel split"
1475 bool "2G/2G user/kernel split"
1477 bool "1G/3G user/kernel split"
1482 default PHYS_OFFSET if !MMU
1483 default 0x40000000 if VMSPLIT_1G
1484 default 0x80000000 if VMSPLIT_2G
1488 int "Maximum number of CPUs (2-32)"
1494 bool "Support for hot-pluggable CPUs"
1497 Say Y here to experiment with turning CPUs off and on. CPUs
1498 can be controlled through /sys/devices/system/cpu.
1501 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1504 Say Y here if you want Linux to communicate with system firmware
1505 implementing the PSCI specification for CPU-centric power
1506 management operations described in ARM document number ARM DEN
1507 0022A ("Power State Coordination Interface System Software on
1510 # The GPIO number here must be sorted by descending number. In case of
1511 # a multiplatform kernel, we just want the highest value required by the
1512 # selected platforms.
1515 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1516 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1517 default 416 if ARCH_SUNXI
1518 default 392 if ARCH_U8500
1519 default 352 if ARCH_VT8500
1520 default 264 if MACH_H4700
1523 Maximum number of GPIOs in the system.
1525 If unsure, leave the default value.
1527 source kernel/Kconfig.preempt
1531 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1532 ARCH_S5PV210 || ARCH_EXYNOS4
1533 default AT91_TIMER_HZ if ARCH_AT91
1534 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1538 depends on HZ_FIXED = 0
1539 prompt "Timer frequency"
1563 default HZ_FIXED if HZ_FIXED != 0
1564 default 100 if HZ_100
1565 default 200 if HZ_200
1566 default 250 if HZ_250
1567 default 300 if HZ_300
1568 default 500 if HZ_500
1572 def_bool HIGH_RES_TIMERS
1574 config THUMB2_KERNEL
1575 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1576 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1577 default y if CPU_THUMBONLY
1579 select ARM_ASM_UNIFIED
1582 By enabling this option, the kernel will be compiled in
1583 Thumb-2 mode. A compiler/assembler that understand the unified
1584 ARM-Thumb syntax is needed.
1588 config THUMB2_AVOID_R_ARM_THM_JUMP11
1589 bool "Work around buggy Thumb-2 short branch relocations in gas"
1590 depends on THUMB2_KERNEL && MODULES
1593 Various binutils versions can resolve Thumb-2 branches to
1594 locally-defined, preemptible global symbols as short-range "b.n"
1595 branch instructions.
1597 This is a problem, because there's no guarantee the final
1598 destination of the symbol, or any candidate locations for a
1599 trampoline, are within range of the branch. For this reason, the
1600 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1601 relocation in modules at all, and it makes little sense to add
1604 The symptom is that the kernel fails with an "unsupported
1605 relocation" error when loading some modules.
1607 Until fixed tools are available, passing
1608 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1609 code which hits this problem, at the cost of a bit of extra runtime
1610 stack usage in some cases.
1612 The problem is described in more detail at:
1613 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1615 Only Thumb-2 kernels are affected.
1617 Unless you are sure your tools don't have this problem, say Y.
1619 config ARM_ASM_UNIFIED
1623 bool "Use the ARM EABI to compile the kernel"
1625 This option allows for the kernel to be compiled using the latest
1626 ARM ABI (aka EABI). This is only useful if you are using a user
1627 space environment that is also compiled with EABI.
1629 Since there are major incompatibilities between the legacy ABI and
1630 EABI, especially with regard to structure member alignment, this
1631 option also changes the kernel syscall calling convention to
1632 disambiguate both ABIs and allow for backward compatibility support
1633 (selected with CONFIG_OABI_COMPAT).
1635 To use this you need GCC version 4.0.0 or later.
1638 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1639 depends on AEABI && !THUMB2_KERNEL
1641 This option preserves the old syscall interface along with the
1642 new (ARM EABI) one. It also provides a compatibility layer to
1643 intercept syscalls that have structure arguments which layout
1644 in memory differs between the legacy ABI and the new ARM EABI
1645 (only for non "thumb" binaries). This option adds a tiny
1646 overhead to all syscalls and produces a slightly larger kernel.
1648 The seccomp filter system will not be available when this is
1649 selected, since there is no way yet to sensibly distinguish
1650 between calling conventions during filtering.
1652 If you know you'll be using only pure EABI user space then you
1653 can say N here. If this option is not selected and you attempt
1654 to execute a legacy ABI binary then the result will be
1655 UNPREDICTABLE (in fact it can be predicted that it won't work
1656 at all). If in doubt say N.
1658 config ARCH_HAS_HOLES_MEMORYMODEL
1661 config ARCH_SPARSEMEM_ENABLE
1664 config ARCH_SPARSEMEM_DEFAULT
1665 def_bool ARCH_SPARSEMEM_ENABLE
1667 config ARCH_SELECT_MEMORY_MODEL
1668 def_bool ARCH_SPARSEMEM_ENABLE
1670 config HAVE_ARCH_PFN_VALID
1671 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1674 bool "High Memory Support"
1677 The address space of ARM processors is only 4 Gigabytes large
1678 and it has to accommodate user address space, kernel address
1679 space as well as some memory mapped IO. That means that, if you
1680 have a large amount of physical memory and/or IO, not all of the
1681 memory can be "permanently mapped" by the kernel. The physical
1682 memory that is not permanently mapped is called "high memory".
1684 Depending on the selected kernel/user memory split, minimum
1685 vmalloc space and actual amount of RAM, you may not need this
1686 option which should result in a slightly faster kernel.
1691 bool "Allocate 2nd-level pagetables from highmem"
1694 config HW_PERF_EVENTS
1695 bool "Enable hardware performance counter support for perf events"
1696 depends on PERF_EVENTS
1699 Enable hardware performance counter support for perf events. If
1700 disabled, perf events will use software events only.
1702 config SYS_SUPPORTS_HUGETLBFS
1706 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1710 config ARCH_WANT_GENERAL_HUGETLB
1715 config FORCE_MAX_ZONEORDER
1716 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1717 range 11 64 if ARCH_SHMOBILE_LEGACY
1718 default "12" if SOC_AM33XX
1719 default "9" if SA1111 || ARCH_EFM32
1722 The kernel memory allocator divides physically contiguous memory
1723 blocks into "zones", where each zone is a power of two number of
1724 pages. This option selects the largest power of two that the kernel
1725 keeps in the memory allocator. If you need to allocate very large
1726 blocks of physically contiguous memory, then you may need to
1727 increase this value.
1729 This config option is actually maximum order plus one. For example,
1730 a value of 11 means that the largest free memory block is 2^10 pages.
1732 config ALIGNMENT_TRAP
1734 depends on CPU_CP15_MMU
1735 default y if !ARCH_EBSA110
1736 select HAVE_PROC_CPU if PROC_FS
1738 ARM processors cannot fetch/store information which is not
1739 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1740 address divisible by 4. On 32-bit ARM processors, these non-aligned
1741 fetch/store instructions will be emulated in software if you say
1742 here, which has a severe performance impact. This is necessary for
1743 correct operation of some network protocols. With an IP-only
1744 configuration it is safe to say N, otherwise say Y.
1746 config UACCESS_WITH_MEMCPY
1747 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1749 default y if CPU_FEROCEON
1751 Implement faster copy_to_user and clear_user methods for CPU
1752 cores where a 8-word STM instruction give significantly higher
1753 memory write throughput than a sequence of individual 32bit stores.
1755 A possible side effect is a slight increase in scheduling latency
1756 between threads sharing the same address space if they invoke
1757 such copy operations with large buffers.
1759 However, if the CPU data cache is using a write-allocate mode,
1760 this option is unlikely to provide any performance gain.
1764 prompt "Enable seccomp to safely compute untrusted bytecode"
1766 This kernel feature is useful for number crunching applications
1767 that may need to compute untrusted bytecode during their
1768 execution. By using pipes or other transports made available to
1769 the process as file descriptors supporting the read/write
1770 syscalls, it's possible to isolate those applications in
1771 their own address space using seccomp. Once seccomp is
1772 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1773 and the task is only allowed to execute a few safe syscalls
1774 defined by each seccomp mode.
1787 bool "Xen guest support on ARM (EXPERIMENTAL)"
1788 depends on ARM && AEABI && OF
1789 depends on CPU_V7 && !CPU_V6
1790 depends on !GENERIC_ATOMIC64
1792 select ARCH_DMA_ADDR_T_64BIT
1796 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1803 bool "Flattened Device Tree support"
1806 select OF_EARLY_FLATTREE
1807 select OF_RESERVED_MEM
1809 Include support for flattened device tree machine descriptions.
1812 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1815 This is the traditional way of passing data to the kernel at boot
1816 time. If you are solely relying on the flattened device tree (or
1817 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1818 to remove ATAGS support from your kernel binary. If unsure,
1821 config DEPRECATED_PARAM_STRUCT
1822 bool "Provide old way to pass kernel parameters"
1825 This was deprecated in 2001 and announced to live on for 5 years.
1826 Some old boot loaders still use this way.
1828 # Compressed boot loader in ROM. Yes, we really want to ask about
1829 # TEXT and BSS so we preserve their values in the config files.
1830 config ZBOOT_ROM_TEXT
1831 hex "Compressed ROM boot loader base address"
1834 The physical address at which the ROM-able zImage is to be
1835 placed in the target. Platforms which normally make use of
1836 ROM-able zImage formats normally set this to a suitable
1837 value in their defconfig file.
1839 If ZBOOT_ROM is not enabled, this has no effect.
1841 config ZBOOT_ROM_BSS
1842 hex "Compressed ROM boot loader BSS address"
1845 The base address of an area of read/write memory in the target
1846 for the ROM-able zImage which must be available while the
1847 decompressor is running. It must be large enough to hold the
1848 entire decompressed kernel plus an additional 128 KiB.
1849 Platforms which normally make use of ROM-able zImage formats
1850 normally set this to a suitable value in their defconfig file.
1852 If ZBOOT_ROM is not enabled, this has no effect.
1855 bool "Compressed boot loader in ROM/flash"
1856 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1857 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1859 Say Y here if you intend to execute your compressed kernel image
1860 (zImage) directly from ROM or flash. If unsure, say N.
1863 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1864 depends on ZBOOT_ROM && ARCH_SH7372
1865 default ZBOOT_ROM_NONE
1867 Include experimental SD/MMC loading code in the ROM-able zImage.
1868 With this enabled it is possible to write the ROM-able zImage
1869 kernel image to an MMC or SD card and boot the kernel straight
1870 from the reset vector. At reset the processor Mask ROM will load
1871 the first part of the ROM-able zImage which in turn loads the
1872 rest the kernel image to RAM.
1874 config ZBOOT_ROM_NONE
1875 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1877 Do not load image from SD or MMC
1879 config ZBOOT_ROM_MMCIF
1880 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1882 Load image from MMCIF hardware block.
1884 config ZBOOT_ROM_SH_MOBILE_SDHI
1885 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1887 Load image from SDHI hardware block
1891 config ARM_APPENDED_DTB
1892 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1895 With this option, the boot code will look for a device tree binary
1896 (DTB) appended to zImage
1897 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1899 This is meant as a backward compatibility convenience for those
1900 systems with a bootloader that can't be upgraded to accommodate
1901 the documented boot protocol using a device tree.
1903 Beware that there is very little in terms of protection against
1904 this option being confused by leftover garbage in memory that might
1905 look like a DTB header after a reboot if no actual DTB is appended
1906 to zImage. Do not leave this option active in a production kernel
1907 if you don't intend to always append a DTB. Proper passing of the
1908 location into r2 of a bootloader provided DTB is always preferable
1911 config ARM_ATAG_DTB_COMPAT
1912 bool "Supplement the appended DTB with traditional ATAG information"
1913 depends on ARM_APPENDED_DTB
1915 Some old bootloaders can't be updated to a DTB capable one, yet
1916 they provide ATAGs with memory configuration, the ramdisk address,
1917 the kernel cmdline string, etc. Such information is dynamically
1918 provided by the bootloader and can't always be stored in a static
1919 DTB. To allow a device tree enabled kernel to be used with such
1920 bootloaders, this option allows zImage to extract the information
1921 from the ATAG list and store it at run time into the appended DTB.
1924 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1925 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1927 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1928 bool "Use bootloader kernel arguments if available"
1930 Uses the command-line options passed by the boot loader instead of
1931 the device tree bootargs property. If the boot loader doesn't provide
1932 any, the device tree bootargs property will be used.
1934 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1935 bool "Extend with bootloader kernel arguments"
1937 The command-line arguments provided by the boot loader will be
1938 appended to the the device tree bootargs property.
1943 string "Default kernel command string"
1946 On some architectures (EBSA110 and CATS), there is currently no way
1947 for the boot loader to pass arguments to the kernel. For these
1948 architectures, you should supply some command-line options at build
1949 time by entering them here. As a minimum, you should specify the
1950 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1953 prompt "Kernel command line type" if CMDLINE != ""
1954 default CMDLINE_FROM_BOOTLOADER
1957 config CMDLINE_FROM_BOOTLOADER
1958 bool "Use bootloader kernel arguments if available"
1960 Uses the command-line options passed by the boot loader. If
1961 the boot loader doesn't provide any, the default kernel command
1962 string provided in CMDLINE will be used.
1964 config CMDLINE_EXTEND
1965 bool "Extend bootloader kernel arguments"
1967 The command-line arguments provided by the boot loader will be
1968 appended to the default kernel command string.
1970 config CMDLINE_FORCE
1971 bool "Always use the default kernel command string"
1973 Always use the default kernel command string, even if the boot
1974 loader passes other arguments to the kernel.
1975 This is useful if you cannot or don't want to change the
1976 command-line options your boot loader passes to the kernel.
1980 bool "Kernel Execute-In-Place from ROM"
1981 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1983 Execute-In-Place allows the kernel to run from non-volatile storage
1984 directly addressable by the CPU, such as NOR flash. This saves RAM
1985 space since the text section of the kernel is not loaded from flash
1986 to RAM. Read-write sections, such as the data section and stack,
1987 are still copied to RAM. The XIP kernel is not compressed since
1988 it has to run directly from flash, so it will take more space to
1989 store it. The flash address used to link the kernel object files,
1990 and for storing it, is configuration dependent. Therefore, if you
1991 say Y here, you must know the proper physical address where to
1992 store the kernel image depending on your own flash memory usage.
1994 Also note that the make target becomes "make xipImage" rather than
1995 "make zImage" or "make Image". The final kernel binary to put in
1996 ROM memory will be arch/arm/boot/xipImage.
2000 config XIP_PHYS_ADDR
2001 hex "XIP Kernel Physical Location"
2002 depends on XIP_KERNEL
2003 default "0x00080000"
2005 This is the physical address in your flash memory the kernel will
2006 be linked for and stored to. This address is dependent on your
2010 bool "Kexec system call (EXPERIMENTAL)"
2011 depends on (!SMP || PM_SLEEP_SMP)
2013 kexec is a system call that implements the ability to shutdown your
2014 current kernel, and to start another kernel. It is like a reboot
2015 but it is independent of the system firmware. And like a reboot
2016 you can start any kernel with it, not just Linux.
2018 It is an ongoing process to be certain the hardware in a machine
2019 is properly shutdown, so do not be surprised if this code does not
2020 initially work for you.
2023 bool "Export atags in procfs"
2024 depends on ATAGS && KEXEC
2027 Should the atags used to boot the kernel be exported in an "atags"
2028 file in procfs. Useful with kexec.
2031 bool "Build kdump crash kernel (EXPERIMENTAL)"
2033 Generate crash dump after being started by kexec. This should
2034 be normally only set in special crash dump kernels which are
2035 loaded in the main kernel with kexec-tools into a specially
2036 reserved region and then later executed after a crash by
2037 kdump/kexec. The crash dump kernel must be compiled to a
2038 memory address not used by the main kernel
2040 For more details see Documentation/kdump/kdump.txt
2042 config AUTO_ZRELADDR
2043 bool "Auto calculation of the decompressed kernel image address"
2045 ZRELADDR is the physical address where the decompressed kernel
2046 image will be placed. If AUTO_ZRELADDR is selected, the address
2047 will be determined at run-time by masking the current IP with
2048 0xf8000000. This assumes the zImage being placed in the first 128MB
2049 from start of memory.
2053 menu "CPU Power Management"
2055 source "drivers/cpufreq/Kconfig"
2057 source "drivers/cpuidle/Kconfig"
2061 menu "Floating point emulation"
2063 comment "At least one emulation must be selected"
2066 bool "NWFPE math emulation"
2067 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2069 Say Y to include the NWFPE floating point emulator in the kernel.
2070 This is necessary to run most binaries. Linux does not currently
2071 support floating point hardware so you need to say Y here even if
2072 your machine has an FPA or floating point co-processor podule.
2074 You may say N here if you are going to load the Acorn FPEmulator
2075 early in the bootup.
2078 bool "Support extended precision"
2079 depends on FPE_NWFPE
2081 Say Y to include 80-bit support in the kernel floating-point
2082 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2083 Note that gcc does not generate 80-bit operations by default,
2084 so in most cases this option only enlarges the size of the
2085 floating point emulator without any good reason.
2087 You almost surely want to say N here.
2090 bool "FastFPE math emulation (EXPERIMENTAL)"
2091 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2093 Say Y here to include the FAST floating point emulator in the kernel.
2094 This is an experimental much faster emulator which now also has full
2095 precision for the mantissa. It does not support any exceptions.
2096 It is very simple, and approximately 3-6 times faster than NWFPE.
2098 It should be sufficient for most programs. It may be not suitable
2099 for scientific calculations, but you have to check this for yourself.
2100 If you do not feel you need a faster FP emulation you should better
2104 bool "VFP-format floating point maths"
2105 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2107 Say Y to include VFP support code in the kernel. This is needed
2108 if your hardware includes a VFP unit.
2110 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2111 release notes and additional status information.
2113 Say N if your target does not have VFP hardware.
2121 bool "Advanced SIMD (NEON) Extension support"
2122 depends on VFPv3 && CPU_V7
2124 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2127 config KERNEL_MODE_NEON
2128 bool "Support for NEON in kernel mode"
2129 depends on NEON && AEABI
2131 Say Y to include support for NEON in kernel mode.
2135 menu "Userspace binary formats"
2137 source "fs/Kconfig.binfmt"
2140 tristate "RISC OS personality"
2143 Say Y here to include the kernel code necessary if you want to run
2144 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2145 experimental; if this sounds frightening, say N and sleep in peace.
2146 You can also say M here to compile this support as a module (which
2147 will be called arthur).
2151 menu "Power management options"
2153 source "kernel/power/Kconfig"
2155 config ARCH_SUSPEND_POSSIBLE
2156 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2157 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2160 config ARM_CPU_SUSPEND
2163 config ARCH_HIBERNATION_POSSIBLE
2166 default y if ARCH_SUSPEND_POSSIBLE
2170 source "net/Kconfig"
2172 source "drivers/Kconfig"
2176 source "arch/arm/Kconfig.debug"
2178 source "security/Kconfig"
2180 source "crypto/Kconfig"
2182 source "lib/Kconfig"
2184 source "arch/arm/kvm/Kconfig"