4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ALLOCATOR
18 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
19 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
20 select GENERIC_IDLE_POLL_SETUP
21 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW
23 select GENERIC_PCI_IOMAP
24 select GENERIC_SCHED_CLOCK
25 select GENERIC_SMP_IDLE_THREAD
26 select GENERIC_STRNCPY_FROM_USER
27 select GENERIC_STRNLEN_USER
28 select HANDLE_DOMAIN_IRQ
29 select HARDIRQS_SW_RESEND
30 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
33 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
34 select HAVE_ARCH_TRACEHOOK
36 select HAVE_CC_STACKPROTECTOR
37 select HAVE_CONTEXT_TRACKING
38 select HAVE_C_RECORDMCOUNT
39 select HAVE_DEBUG_KMEMLEAK
40 select HAVE_DMA_API_DEBUG
42 select HAVE_DMA_CONTIGUOUS if MMU
43 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
44 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
45 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
46 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
47 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
48 select HAVE_GENERIC_DMA_COHERENT
49 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
50 select HAVE_IDE if PCI || ISA || PCMCIA
51 select HAVE_IRQ_TIME_ACCOUNTING
52 select HAVE_KERNEL_GZIP
53 select HAVE_KERNEL_LZ4
54 select HAVE_KERNEL_LZMA
55 select HAVE_KERNEL_LZO
57 select HAVE_KPROBES if !XIP_KERNEL
58 select HAVE_KRETPROBES if (HAVE_KPROBES)
60 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
61 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
62 select HAVE_PERF_EVENTS
64 select HAVE_PERF_USER_STACK_DUMP
65 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
66 select HAVE_REGS_AND_STACK_ACCESS_API
67 select HAVE_SYSCALL_TRACEPOINTS
69 select HAVE_VIRT_CPU_ACCOUNTING_GEN
70 select IRQ_FORCED_THREADING
71 select MODULES_USE_ELF_REL
74 select OLD_SIGSUSPEND3
75 select PERF_USE_VMALLOC
77 select SYS_SUPPORTS_APM_EMULATION
78 # Above selects are sorted alphabetically; please add new ones
79 # according to that. Thanks.
81 The ARM series is a line of low-power-consumption RISC chip designs
82 licensed by ARM Ltd and targeted at embedded applications and
83 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
84 manufactured, but legacy ARM-based PC hardware remains popular in
85 Europe. There is an ARM Linux project with a web page at
86 <http://www.arm.linux.org.uk/>.
88 config ARM_HAS_SG_CHAIN
89 select ARCH_HAS_SG_CHAIN
92 config NEED_SG_DMA_LENGTH
95 config ARM_DMA_USE_IOMMU
97 select ARM_HAS_SG_CHAIN
98 select NEED_SG_DMA_LENGTH
102 config ARM_DMA_IOMMU_ALIGNMENT
103 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
107 DMA mapping framework by default aligns all buffers to the smallest
108 PAGE_SIZE order which is greater than or equal to the requested buffer
109 size. This works well for buffers up to a few hundreds kilobytes, but
110 for larger buffers it just a waste of address space. Drivers which has
111 relatively small addressing window (like 64Mib) might run out of
112 virtual space with just a few allocations.
114 With this parameter you can specify the maximum PAGE_SIZE order for
115 DMA IOMMU buffers. Larger buffers will be aligned only to this
116 specified order. The order is expressed as a power of two multiplied
121 config MIGHT_HAVE_PCI
124 config SYS_SUPPORTS_APM_EMULATION
129 select GENERIC_ALLOCATOR
140 The Extended Industry Standard Architecture (EISA) bus was
141 developed as an open alternative to the IBM MicroChannel bus.
143 The EISA bus provided some of the features of the IBM MicroChannel
144 bus while maintaining backward compatibility with cards made for
145 the older ISA bus. The EISA bus saw limited use between 1988 and
146 1995 when it was made obsolete by the PCI bus.
148 Say Y here if you are building a kernel for an EISA-based machine.
155 config STACKTRACE_SUPPORT
159 config HAVE_LATENCYTOP_SUPPORT
164 config LOCKDEP_SUPPORT
168 config TRACE_IRQFLAGS_SUPPORT
172 config RWSEM_XCHGADD_ALGORITHM
176 config ARCH_HAS_ILOG2_U32
179 config ARCH_HAS_ILOG2_U64
182 config ARCH_HAS_BANDGAP
185 config GENERIC_HWEIGHT
189 config GENERIC_CALIBRATE_DELAY
193 config ARCH_MAY_HAVE_PC_FDC
199 config NEED_DMA_MAP_STATE
202 config ARCH_SUPPORTS_UPROBES
205 config ARCH_HAS_DMA_SET_COHERENT_MASK
208 config GENERIC_ISA_DMA
214 config NEED_RET_TO_USER
222 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
223 default DRAM_BASE if REMAP_VECTORS_TO_RAM
226 The base address of exception vectors. This must be two pages
229 config ARM_PATCH_PHYS_VIRT
230 bool "Patch physical to virtual translations at runtime" if EMBEDDED
232 depends on !XIP_KERNEL && MMU
233 depends on !ARCH_REALVIEW || !SPARSEMEM
235 Patch phys-to-virt and virt-to-phys translation functions at
236 boot and module load time according to the position of the
237 kernel in system memory.
239 This can only be used with non-XIP MMU kernels where the base
240 of physical memory is at a 16MB boundary.
242 Only disable this option if you know that you do not require
243 this feature (eg, building a kernel for a single machine) and
244 you need to shrink the kernel to the minimal size.
246 config NEED_MACH_IO_H
249 Select this when mach/io.h is required to provide special
250 definitions for this platform. The need for mach/io.h should
251 be avoided when possible.
253 config NEED_MACH_MEMORY_H
256 Select this when mach/memory.h is required to provide special
257 definitions for this platform. The need for mach/memory.h should
258 be avoided when possible.
261 hex "Physical address of main memory" if MMU
262 depends on !ARM_PATCH_PHYS_VIRT
263 default DRAM_BASE if !MMU
264 default 0x00000000 if ARCH_EBSA110 || \
265 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
270 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
271 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
272 default 0x20000000 if ARCH_S5PV210
273 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
274 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
275 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
276 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
277 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
279 Please provide the physical address corresponding to the
280 location of main memory in your system.
286 source "init/Kconfig"
288 source "kernel/Kconfig.freezer"
293 bool "MMU-based Paged Memory Management Support"
296 Select if you want MMU-based virtualised addressing space
297 support by paged memory management. If unsure, say 'Y'.
300 # The "ARM system type" choice list is ordered alphabetically by option
301 # text. Please add new entries in the option alphabetic order.
304 prompt "ARM system type"
305 default ARCH_VERSATILE if !MMU
306 default ARCH_MULTIPLATFORM if MMU
308 config ARCH_MULTIPLATFORM
309 bool "Allow multiple platforms to be selected"
311 select ARCH_WANT_OPTIONAL_GPIOLIB
312 select ARM_HAS_SG_CHAIN
313 select ARM_PATCH_PHYS_VIRT
317 select GENERIC_CLOCKEVENTS
318 select MIGHT_HAVE_PCI
319 select MULTI_IRQ_HANDLER
323 config ARCH_INTEGRATOR
324 bool "ARM Ltd. Integrator family"
326 select ARM_PATCH_PHYS_VIRT if MMU
329 select COMMON_CLK_VERSATILE
330 select GENERIC_CLOCKEVENTS
333 select MULTI_IRQ_HANDLER
334 select PLAT_VERSATILE
337 select VERSATILE_FPGA_IRQ
339 Support for ARM's Integrator platform.
342 bool "ARM Ltd. RealView family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_TIMER_SP804
347 select COMMON_CLK_VERSATILE
348 select GENERIC_CLOCKEVENTS
349 select GPIO_PL061 if GPIOLIB
351 select NEED_MACH_MEMORY_H
352 select PLAT_VERSATILE
353 select PLAT_VERSATILE_SCHED_CLOCK
355 This enables support for ARM Ltd RealView boards.
357 config ARCH_VERSATILE
358 bool "ARM Ltd. Versatile family"
359 select ARCH_WANT_OPTIONAL_GPIOLIB
361 select ARM_TIMER_SP804
364 select GENERIC_CLOCKEVENTS
365 select HAVE_MACH_CLKDEV
367 select PLAT_VERSATILE
368 select PLAT_VERSATILE_CLOCK
369 select PLAT_VERSATILE_SCHED_CLOCK
370 select VERSATILE_FPGA_IRQ
372 This enables support for ARM Ltd Versatile board.
376 select ARCH_REQUIRE_GPIOLIB
379 select NEED_MACH_IO_H if PCCARD
384 This enables support for systems based on Atmel
385 AT91RM9200, AT91SAM9 and SAMA5 processors.
388 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
389 select ARCH_REQUIRE_GPIOLIB
394 select GENERIC_CLOCKEVENTS
398 Support for Cirrus Logic 711x/721x/731x based boards.
401 bool "Cortina Systems Gemini"
402 select ARCH_REQUIRE_GPIOLIB
405 select GENERIC_CLOCKEVENTS
407 Support for the Cortina Systems Gemini family SoCs
411 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_IO_H
415 select NEED_MACH_MEMORY_H
418 This is an evaluation board for the StrongARM processor available
419 from Digital. It has limited hardware on-board, including an
420 Ethernet interface, two PCMCIA sockets, two serial ports and a
424 bool "Energy Micro efm32"
426 select ARCH_REQUIRE_GPIOLIB
432 select GENERIC_CLOCKEVENTS
438 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
443 select ARCH_HAS_HOLES_MEMORYMODEL
444 select ARCH_REQUIRE_GPIOLIB
445 select ARCH_USES_GETTIMEOFFSET
451 This enables support for the Cirrus EP93xx series of CPUs.
453 config ARCH_FOOTBRIDGE
457 select GENERIC_CLOCKEVENTS
459 select NEED_MACH_IO_H if !MMU
460 select NEED_MACH_MEMORY_H
462 Support for systems based on the DC21285 companion chip
463 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
466 bool "Hilscher NetX based"
470 select GENERIC_CLOCKEVENTS
472 This enables support for systems based on the Hilscher NetX Soc
478 select NEED_MACH_MEMORY_H
479 select NEED_RET_TO_USER
485 Support for Intel's IOP13XX (XScale) family of processors.
490 select ARCH_REQUIRE_GPIOLIB
493 select NEED_RET_TO_USER
497 Support for Intel's 80219 and IOP32X (XScale) family of
503 select ARCH_REQUIRE_GPIOLIB
506 select NEED_RET_TO_USER
510 Support for Intel's IOP33X (XScale) family of processors.
515 select ARCH_HAS_DMA_SET_COHERENT_MASK
516 select ARCH_REQUIRE_GPIOLIB
517 select ARCH_SUPPORTS_BIG_ENDIAN
520 select DMABOUNCE if PCI
521 select GENERIC_CLOCKEVENTS
522 select MIGHT_HAVE_PCI
523 select NEED_MACH_IO_H
524 select USB_EHCI_BIG_ENDIAN_DESC
525 select USB_EHCI_BIG_ENDIAN_MMIO
527 Support for Intel's IXP4XX (XScale) family of processors.
531 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
534 select MIGHT_HAVE_PCI
538 select PLAT_ORION_LEGACY
540 Support for the Marvell Dove SoC 88AP510
543 bool "Marvell MV78xx0"
544 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_CLOCKEVENTS
549 select PLAT_ORION_LEGACY
551 Support for the following Marvell MV78xx0 series SoCs:
557 select ARCH_REQUIRE_GPIOLIB
559 select GENERIC_CLOCKEVENTS
562 select PLAT_ORION_LEGACY
564 Support for the following Marvell Orion 5x series SoCs:
565 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
566 Orion-2 (5281), Orion-1-90 (6183).
569 bool "Marvell PXA168/910/MMP2"
571 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_ALLOCATOR
574 select GENERIC_CLOCKEVENTS
577 select MULTI_IRQ_HANDLER
582 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
585 bool "Micrel/Kendin KS8695"
586 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_CLOCKEVENTS
590 select NEED_MACH_MEMORY_H
592 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
593 System-on-Chip devices.
596 bool "Nuvoton W90X900 CPU"
597 select ARCH_REQUIRE_GPIOLIB
601 select GENERIC_CLOCKEVENTS
603 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
604 At present, the w90x900 has been renamed nuc900, regarding
605 the ARM series product line, you can login the following
606 link address to know more.
608 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
609 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
613 select ARCH_REQUIRE_GPIOLIB
618 select GENERIC_CLOCKEVENTS
622 Support for the NXP LPC32XX family of processors
625 bool "PXA2xx/PXA3xx-based"
628 select ARCH_REQUIRE_GPIOLIB
629 select ARM_CPU_SUSPEND if PM
634 select GENERIC_CLOCKEVENTS
637 select MULTI_IRQ_HANDLER
641 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
644 bool "Qualcomm MSM (non-multiplatform)"
645 select ARCH_REQUIRE_GPIOLIB
647 select GENERIC_CLOCKEVENTS
649 Support for Qualcomm MSM/QSD based systems. This runs on the
650 apps processor of the MSM/QSD and depends on a shared memory
651 interface to the modem processor which runs the baseband
652 stack and controls some vital subsystems
653 (clock and power control, etc).
655 config ARCH_SHMOBILE_LEGACY
656 bool "Renesas ARM SoCs (non-multiplatform)"
658 select ARM_PATCH_PHYS_VIRT if MMU
661 select GENERIC_CLOCKEVENTS
662 select HAVE_ARM_SCU if SMP
663 select HAVE_ARM_TWD if SMP
664 select HAVE_MACH_CLKDEV
666 select MIGHT_HAVE_CACHE_L2X0
667 select MULTI_IRQ_HANDLER
670 select PM_GENERIC_DOMAINS if PM
674 Support for Renesas ARM SoC platforms using a non-multiplatform
675 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
681 select ARCH_MAY_HAVE_PC_FDC
682 select ARCH_SPARSEMEM_ENABLE
683 select ARCH_USES_GETTIMEOFFSET
687 select HAVE_PATA_PLATFORM
689 select NEED_MACH_IO_H
690 select NEED_MACH_MEMORY_H
694 On the Acorn Risc-PC, Linux can support the internal IDE disk and
695 CD-ROM interface, serial and parallel port, and the floppy drive.
700 select ARCH_REQUIRE_GPIOLIB
701 select ARCH_SPARSEMEM_ENABLE
706 select GENERIC_CLOCKEVENTS
709 select NEED_MACH_MEMORY_H
712 Support for StrongARM 11x0 based boards.
715 bool "Samsung S3C24XX SoCs"
716 select ARCH_REQUIRE_GPIOLIB
719 select CLKSRC_SAMSUNG_PWM
720 select GENERIC_CLOCKEVENTS
722 select HAVE_S3C2410_I2C if I2C
723 select HAVE_S3C2410_WATCHDOG if WATCHDOG
724 select HAVE_S3C_RTC if RTC_CLASS
725 select MULTI_IRQ_HANDLER
726 select NEED_MACH_IO_H
729 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
730 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
731 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
732 Samsung SMDK2410 development board (and derivatives).
735 bool "Samsung S3C64XX"
736 select ARCH_REQUIRE_GPIOLIB
741 select CLKSRC_SAMSUNG_PWM
742 select COMMON_CLK_SAMSUNG
744 select GENERIC_CLOCKEVENTS
746 select HAVE_S3C2410_I2C if I2C
747 select HAVE_S3C2410_WATCHDOG if WATCHDOG
751 select PM_GENERIC_DOMAINS if PM
753 select S3C_GPIO_TRACK
755 select SAMSUNG_WAKEMASK
756 select SAMSUNG_WDT_RESET
758 Samsung S3C64XX series based systems
762 select ARCH_HAS_HOLES_MEMORYMODEL
763 select ARCH_REQUIRE_GPIOLIB
765 select GENERIC_ALLOCATOR
766 select GENERIC_CLOCKEVENTS
767 select GENERIC_IRQ_CHIP
773 Support for TI's DaVinci platform.
778 select ARCH_HAS_HOLES_MEMORYMODEL
780 select ARCH_REQUIRE_GPIOLIB
783 select GENERIC_CLOCKEVENTS
784 select GENERIC_IRQ_CHIP
787 select NEED_MACH_IO_H if PCCARD
788 select NEED_MACH_MEMORY_H
790 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
794 menu "Multiple platform selection"
795 depends on ARCH_MULTIPLATFORM
797 comment "CPU Core family selection"
800 bool "ARMv4 based platforms (FA526)"
801 depends on !ARCH_MULTI_V6_V7
802 select ARCH_MULTI_V4_V5
805 config ARCH_MULTI_V4T
806 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
807 depends on !ARCH_MULTI_V6_V7
808 select ARCH_MULTI_V4_V5
809 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
810 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
811 CPU_ARM925T || CPU_ARM940T)
814 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
815 depends on !ARCH_MULTI_V6_V7
816 select ARCH_MULTI_V4_V5
817 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
818 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
819 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
821 config ARCH_MULTI_V4_V5
825 bool "ARMv6 based platforms (ARM11)"
826 select ARCH_MULTI_V6_V7
830 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
832 select ARCH_MULTI_V6_V7
836 config ARCH_MULTI_V6_V7
838 select MIGHT_HAVE_CACHE_L2X0
840 config ARCH_MULTI_CPU_AUTO
841 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
847 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
851 select HAVE_ARM_ARCH_TIMER
854 # This is sorted alphabetically by mach-* pathname. However, plat-*
855 # Kconfigs may be included either alphabetically (according to the
856 # plat- suffix) or along side the corresponding mach-* source.
858 source "arch/arm/mach-mvebu/Kconfig"
860 source "arch/arm/mach-at91/Kconfig"
862 source "arch/arm/mach-axxia/Kconfig"
864 source "arch/arm/mach-bcm/Kconfig"
866 source "arch/arm/mach-berlin/Kconfig"
868 source "arch/arm/mach-clps711x/Kconfig"
870 source "arch/arm/mach-cns3xxx/Kconfig"
872 source "arch/arm/mach-davinci/Kconfig"
874 source "arch/arm/mach-dove/Kconfig"
876 source "arch/arm/mach-ep93xx/Kconfig"
878 source "arch/arm/mach-footbridge/Kconfig"
880 source "arch/arm/mach-gemini/Kconfig"
882 source "arch/arm/mach-highbank/Kconfig"
884 source "arch/arm/mach-hisi/Kconfig"
886 source "arch/arm/mach-integrator/Kconfig"
888 source "arch/arm/mach-iop32x/Kconfig"
890 source "arch/arm/mach-iop33x/Kconfig"
892 source "arch/arm/mach-iop13xx/Kconfig"
894 source "arch/arm/mach-ixp4xx/Kconfig"
896 source "arch/arm/mach-keystone/Kconfig"
898 source "arch/arm/mach-ks8695/Kconfig"
900 source "arch/arm/mach-meson/Kconfig"
902 source "arch/arm/mach-msm/Kconfig"
904 source "arch/arm/mach-moxart/Kconfig"
906 source "arch/arm/mach-mv78xx0/Kconfig"
908 source "arch/arm/mach-imx/Kconfig"
910 source "arch/arm/mach-mediatek/Kconfig"
912 source "arch/arm/mach-mxs/Kconfig"
914 source "arch/arm/mach-netx/Kconfig"
916 source "arch/arm/mach-nomadik/Kconfig"
918 source "arch/arm/mach-nspire/Kconfig"
920 source "arch/arm/plat-omap/Kconfig"
922 source "arch/arm/mach-omap1/Kconfig"
924 source "arch/arm/mach-omap2/Kconfig"
926 source "arch/arm/mach-orion5x/Kconfig"
928 source "arch/arm/mach-picoxcell/Kconfig"
930 source "arch/arm/mach-pxa/Kconfig"
931 source "arch/arm/plat-pxa/Kconfig"
933 source "arch/arm/mach-mmp/Kconfig"
935 source "arch/arm/mach-qcom/Kconfig"
937 source "arch/arm/mach-realview/Kconfig"
939 source "arch/arm/mach-rockchip/Kconfig"
941 source "arch/arm/mach-sa1100/Kconfig"
943 source "arch/arm/mach-socfpga/Kconfig"
945 source "arch/arm/mach-spear/Kconfig"
947 source "arch/arm/mach-sti/Kconfig"
949 source "arch/arm/mach-s3c24xx/Kconfig"
951 source "arch/arm/mach-s3c64xx/Kconfig"
953 source "arch/arm/mach-s5pv210/Kconfig"
955 source "arch/arm/mach-exynos/Kconfig"
956 source "arch/arm/plat-samsung/Kconfig"
958 source "arch/arm/mach-shmobile/Kconfig"
960 source "arch/arm/mach-sunxi/Kconfig"
962 source "arch/arm/mach-prima2/Kconfig"
964 source "arch/arm/mach-tegra/Kconfig"
966 source "arch/arm/mach-u300/Kconfig"
968 source "arch/arm/mach-ux500/Kconfig"
970 source "arch/arm/mach-versatile/Kconfig"
972 source "arch/arm/mach-vexpress/Kconfig"
973 source "arch/arm/plat-versatile/Kconfig"
975 source "arch/arm/mach-vt8500/Kconfig"
977 source "arch/arm/mach-w90x900/Kconfig"
979 source "arch/arm/mach-zynq/Kconfig"
981 # Definitions to make life easier
987 select GENERIC_CLOCKEVENTS
993 select GENERIC_IRQ_CHIP
996 config PLAT_ORION_LEGACY
1003 config PLAT_VERSATILE
1006 config ARM_TIMER_SP804
1009 select CLKSRC_OF if OF
1011 source "arch/arm/firmware/Kconfig"
1013 source arch/arm/mm/Kconfig
1016 bool "Enable iWMMXt support"
1017 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1018 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1020 Enable support for iWMMXt context switching at run time if
1021 running on a CPU that supports it.
1023 config MULTI_IRQ_HANDLER
1026 Allow each machine to specify it's own IRQ handler at run time.
1029 source "arch/arm/Kconfig-nommu"
1032 config PJ4B_ERRATA_4742
1033 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1034 depends on CPU_PJ4B && MACH_ARMADA_370
1037 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1038 Event (WFE) IDLE states, a specific timing sensitivity exists between
1039 the retiring WFI/WFE instructions and the newly issued subsequent
1040 instructions. This sensitivity can result in a CPU hang scenario.
1042 The software must insert either a Data Synchronization Barrier (DSB)
1043 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1046 config ARM_ERRATA_326103
1047 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1050 Executing a SWP instruction to read-only memory does not set bit 11
1051 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1052 treat the access as a read, preventing a COW from occurring and
1053 causing the faulting task to livelock.
1055 config ARM_ERRATA_411920
1056 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1057 depends on CPU_V6 || CPU_V6K
1059 Invalidation of the Instruction Cache operation can
1060 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1061 It does not affect the MPCore. This option enables the ARM Ltd.
1062 recommended workaround.
1064 config ARM_ERRATA_430973
1065 bool "ARM errata: Stale prediction on replaced interworking branch"
1068 This option enables the workaround for the 430973 Cortex-A8
1069 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1070 interworking branch is replaced with another code sequence at the
1071 same virtual address, whether due to self-modifying code or virtual
1072 to physical address re-mapping, Cortex-A8 does not recover from the
1073 stale interworking branch prediction. This results in Cortex-A8
1074 executing the new code sequence in the incorrect ARM or Thumb state.
1075 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1076 and also flushes the branch target cache at every context switch.
1077 Note that setting specific bits in the ACTLR register may not be
1078 available in non-secure mode.
1080 config ARM_ERRATA_458693
1081 bool "ARM errata: Processor deadlock when a false hazard is created"
1083 depends on !ARCH_MULTIPLATFORM
1085 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1086 erratum. For very specific sequences of memory operations, it is
1087 possible for a hazard condition intended for a cache line to instead
1088 be incorrectly associated with a different cache line. This false
1089 hazard might then cause a processor deadlock. The workaround enables
1090 the L1 caching of the NEON accesses and disables the PLD instruction
1091 in the ACTLR register. Note that setting specific bits in the ACTLR
1092 register may not be available in non-secure mode.
1094 config ARM_ERRATA_460075
1095 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1097 depends on !ARCH_MULTIPLATFORM
1099 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1100 erratum. Any asynchronous access to the L2 cache may encounter a
1101 situation in which recent store transactions to the L2 cache are lost
1102 and overwritten with stale memory contents from external memory. The
1103 workaround disables the write-allocate mode for the L2 cache via the
1104 ACTLR register. Note that setting specific bits in the ACTLR register
1105 may not be available in non-secure mode.
1107 config ARM_ERRATA_742230
1108 bool "ARM errata: DMB operation may be faulty"
1109 depends on CPU_V7 && SMP
1110 depends on !ARCH_MULTIPLATFORM
1112 This option enables the workaround for the 742230 Cortex-A9
1113 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1114 between two write operations may not ensure the correct visibility
1115 ordering of the two writes. This workaround sets a specific bit in
1116 the diagnostic register of the Cortex-A9 which causes the DMB
1117 instruction to behave as a DSB, ensuring the correct behaviour of
1120 config ARM_ERRATA_742231
1121 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1122 depends on CPU_V7 && SMP
1123 depends on !ARCH_MULTIPLATFORM
1125 This option enables the workaround for the 742231 Cortex-A9
1126 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1127 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1128 accessing some data located in the same cache line, may get corrupted
1129 data due to bad handling of the address hazard when the line gets
1130 replaced from one of the CPUs at the same time as another CPU is
1131 accessing it. This workaround sets specific bits in the diagnostic
1132 register of the Cortex-A9 which reduces the linefill issuing
1133 capabilities of the processor.
1135 config ARM_ERRATA_643719
1136 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1137 depends on CPU_V7 && SMP
1139 This option enables the workaround for the 643719 Cortex-A9 (prior to
1140 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1141 register returns zero when it should return one. The workaround
1142 corrects this value, ensuring cache maintenance operations which use
1143 it behave as intended and avoiding data corruption.
1145 config ARM_ERRATA_720789
1146 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1149 This option enables the workaround for the 720789 Cortex-A9 (prior to
1150 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1151 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1152 As a consequence of this erratum, some TLB entries which should be
1153 invalidated are not, resulting in an incoherency in the system page
1154 tables. The workaround changes the TLB flushing routines to invalidate
1155 entries regardless of the ASID.
1157 config ARM_ERRATA_743622
1158 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1160 depends on !ARCH_MULTIPLATFORM
1162 This option enables the workaround for the 743622 Cortex-A9
1163 (r2p*) erratum. Under very rare conditions, a faulty
1164 optimisation in the Cortex-A9 Store Buffer may lead to data
1165 corruption. This workaround sets a specific bit in the diagnostic
1166 register of the Cortex-A9 which disables the Store Buffer
1167 optimisation, preventing the defect from occurring. This has no
1168 visible impact on the overall performance or power consumption of the
1171 config ARM_ERRATA_751472
1172 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1174 depends on !ARCH_MULTIPLATFORM
1176 This option enables the workaround for the 751472 Cortex-A9 (prior
1177 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1178 completion of a following broadcasted operation if the second
1179 operation is received by a CPU before the ICIALLUIS has completed,
1180 potentially leading to corrupted entries in the cache or TLB.
1182 config ARM_ERRATA_754322
1183 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1186 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1187 r3p*) erratum. A speculative memory access may cause a page table walk
1188 which starts prior to an ASID switch but completes afterwards. This
1189 can populate the micro-TLB with a stale entry which may be hit with
1190 the new ASID. This workaround places two dsb instructions in the mm
1191 switching code so that no page table walks can cross the ASID switch.
1193 config ARM_ERRATA_754327
1194 bool "ARM errata: no automatic Store Buffer drain"
1195 depends on CPU_V7 && SMP
1197 This option enables the workaround for the 754327 Cortex-A9 (prior to
1198 r2p0) erratum. The Store Buffer does not have any automatic draining
1199 mechanism and therefore a livelock may occur if an external agent
1200 continuously polls a memory location waiting to observe an update.
1201 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1202 written polling loops from denying visibility of updates to memory.
1204 config ARM_ERRATA_364296
1205 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1208 This options enables the workaround for the 364296 ARM1136
1209 r0p2 erratum (possible cache data corruption with
1210 hit-under-miss enabled). It sets the undocumented bit 31 in
1211 the auxiliary control register and the FI bit in the control
1212 register, thus disabling hit-under-miss without putting the
1213 processor into full low interrupt latency mode. ARM11MPCore
1216 config ARM_ERRATA_764369
1217 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1218 depends on CPU_V7 && SMP
1220 This option enables the workaround for erratum 764369
1221 affecting Cortex-A9 MPCore with two or more processors (all
1222 current revisions). Under certain timing circumstances, a data
1223 cache line maintenance operation by MVA targeting an Inner
1224 Shareable memory region may fail to proceed up to either the
1225 Point of Coherency or to the Point of Unification of the
1226 system. This workaround adds a DSB instruction before the
1227 relevant cache maintenance functions and sets a specific bit
1228 in the diagnostic control register of the SCU.
1230 config ARM_ERRATA_775420
1231 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1234 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1235 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1236 operation aborts with MMU exception, it might cause the processor
1237 to deadlock. This workaround puts DSB before executing ISB if
1238 an abort may occur on cache maintenance.
1240 config ARM_ERRATA_798181
1241 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1242 depends on CPU_V7 && SMP
1244 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1245 adequately shooting down all use of the old entries. This
1246 option enables the Linux kernel workaround for this erratum
1247 which sends an IPI to the CPUs that are running the same ASID
1248 as the one being invalidated.
1250 config ARM_ERRATA_773022
1251 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1254 This option enables the workaround for the 773022 Cortex-A15
1255 (up to r0p4) erratum. In certain rare sequences of code, the
1256 loop buffer may deliver incorrect instructions. This
1257 workaround disables the loop buffer to avoid the erratum.
1261 source "arch/arm/common/Kconfig"
1271 Find out whether you have ISA slots on your motherboard. ISA is the
1272 name of a bus system, i.e. the way the CPU talks to the other stuff
1273 inside your box. Other bus systems are PCI, EISA, MicroChannel
1274 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1275 newer boards don't support it. If you have ISA, say Y, otherwise N.
1277 # Select ISA DMA controller support
1282 # Select ISA DMA interface
1287 bool "PCI support" if MIGHT_HAVE_PCI
1289 Find out whether you have a PCI motherboard. PCI is the name of a
1290 bus system, i.e. the way the CPU talks to the other stuff inside
1291 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1292 VESA. If you have PCI, say Y, otherwise N.
1298 config PCI_NANOENGINE
1299 bool "BSE nanoEngine PCI support"
1300 depends on SA1100_NANOENGINE
1302 Enable PCI on the BSE nanoEngine board.
1307 config PCI_HOST_ITE8152
1309 depends on PCI && MACH_ARMCORE
1313 source "drivers/pci/Kconfig"
1314 source "drivers/pci/pcie/Kconfig"
1316 source "drivers/pcmcia/Kconfig"
1320 menu "Kernel Features"
1325 This option should be selected by machines which have an SMP-
1328 The only effect of this option is to make the SMP-related
1329 options available to the user for configuration.
1332 bool "Symmetric Multi-Processing"
1333 depends on CPU_V6K || CPU_V7
1334 depends on GENERIC_CLOCKEVENTS
1336 depends on MMU || ARM_MPU
1338 This enables support for systems with more than one CPU. If you have
1339 a system with only one CPU, say N. If you have a system with more
1340 than one CPU, say Y.
1342 If you say N here, the kernel will run on uni- and multiprocessor
1343 machines, but will use only one CPU of a multiprocessor machine. If
1344 you say Y here, the kernel will run on many, but not all,
1345 uniprocessor machines. On a uniprocessor machine, the kernel
1346 will run faster if you say N here.
1348 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1349 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1350 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1352 If you don't know what to do here, say N.
1355 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1356 depends on SMP && !XIP_KERNEL && MMU
1359 SMP kernels contain instructions which fail on non-SMP processors.
1360 Enabling this option allows the kernel to modify itself to make
1361 these instructions safe. Disabling it allows about 1K of space
1364 If you don't know what to do here, say Y.
1366 config ARM_CPU_TOPOLOGY
1367 bool "Support cpu topology definition"
1368 depends on SMP && CPU_V7
1371 Support ARM cpu topology definition. The MPIDR register defines
1372 affinity between processors which is then used to describe the cpu
1373 topology of an ARM System.
1376 bool "Multi-core scheduler support"
1377 depends on ARM_CPU_TOPOLOGY
1379 Multi-core scheduler support improves the CPU scheduler's decision
1380 making when dealing with multi-core CPU chips at a cost of slightly
1381 increased overhead in some places. If unsure say N here.
1384 bool "SMT scheduler support"
1385 depends on ARM_CPU_TOPOLOGY
1387 Improves the CPU scheduler's decision making when dealing with
1388 MultiThreading at a cost of slightly increased overhead in some
1389 places. If unsure say N here.
1394 This option enables support for the ARM system coherency unit
1396 config HAVE_ARM_ARCH_TIMER
1397 bool "Architected timer support"
1399 select ARM_ARCH_TIMER
1400 select GENERIC_CLOCKEVENTS
1402 This option enables support for the ARM architected timer
1407 select CLKSRC_OF if OF
1409 This options enables support for the ARM timer and watchdog unit
1412 bool "Multi-Cluster Power Management"
1413 depends on CPU_V7 && SMP
1415 This option provides the common power management infrastructure
1416 for (multi-)cluster based systems, such as big.LITTLE based
1419 config MCPM_QUAD_CLUSTER
1423 To avoid wasting resources unnecessarily, MCPM only supports up
1424 to 2 clusters by default.
1425 Platforms with 3 or 4 clusters that use MCPM must select this
1426 option to allow the additional clusters to be managed.
1429 bool "big.LITTLE support (Experimental)"
1430 depends on CPU_V7 && SMP
1433 This option enables support selections for the big.LITTLE
1434 system architecture.
1437 bool "big.LITTLE switcher support"
1438 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1439 select ARM_CPU_SUSPEND
1442 The big.LITTLE "switcher" provides the core functionality to
1443 transparently handle transition between a cluster of A15's
1444 and a cluster of A7's in a big.LITTLE system.
1446 config BL_SWITCHER_DUMMY_IF
1447 tristate "Simple big.LITTLE switcher user interface"
1448 depends on BL_SWITCHER && DEBUG_KERNEL
1450 This is a simple and dummy char dev interface to control
1451 the big.LITTLE switcher core code. It is meant for
1452 debugging purposes only.
1455 prompt "Memory split"
1459 Select the desired split between kernel and user memory.
1461 If you are not absolutely sure what you are doing, leave this
1465 bool "3G/1G user/kernel split"
1467 bool "2G/2G user/kernel split"
1469 bool "1G/3G user/kernel split"
1474 default PHYS_OFFSET if !MMU
1475 default 0x40000000 if VMSPLIT_1G
1476 default 0x80000000 if VMSPLIT_2G
1480 int "Maximum number of CPUs (2-32)"
1486 bool "Support for hot-pluggable CPUs"
1489 Say Y here to experiment with turning CPUs off and on. CPUs
1490 can be controlled through /sys/devices/system/cpu.
1493 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1496 Say Y here if you want Linux to communicate with system firmware
1497 implementing the PSCI specification for CPU-centric power
1498 management operations described in ARM document number ARM DEN
1499 0022A ("Power State Coordination Interface System Software on
1502 # The GPIO number here must be sorted by descending number. In case of
1503 # a multiplatform kernel, we just want the highest value required by the
1504 # selected platforms.
1507 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1508 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1509 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1510 default 416 if ARCH_SUNXI
1511 default 392 if ARCH_U8500
1512 default 352 if ARCH_VT8500
1513 default 288 if ARCH_ROCKCHIP
1514 default 264 if MACH_H4700
1517 Maximum number of GPIOs in the system.
1519 If unsure, leave the default value.
1521 source kernel/Kconfig.preempt
1525 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1526 ARCH_S5PV210 || ARCH_EXYNOS4
1527 default AT91_TIMER_HZ if ARCH_AT91
1528 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1532 depends on HZ_FIXED = 0
1533 prompt "Timer frequency"
1557 default HZ_FIXED if HZ_FIXED != 0
1558 default 100 if HZ_100
1559 default 200 if HZ_200
1560 default 250 if HZ_250
1561 default 300 if HZ_300
1562 default 500 if HZ_500
1566 def_bool HIGH_RES_TIMERS
1568 config THUMB2_KERNEL
1569 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1570 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1571 default y if CPU_THUMBONLY
1573 select ARM_ASM_UNIFIED
1576 By enabling this option, the kernel will be compiled in
1577 Thumb-2 mode. A compiler/assembler that understand the unified
1578 ARM-Thumb syntax is needed.
1582 config THUMB2_AVOID_R_ARM_THM_JUMP11
1583 bool "Work around buggy Thumb-2 short branch relocations in gas"
1584 depends on THUMB2_KERNEL && MODULES
1587 Various binutils versions can resolve Thumb-2 branches to
1588 locally-defined, preemptible global symbols as short-range "b.n"
1589 branch instructions.
1591 This is a problem, because there's no guarantee the final
1592 destination of the symbol, or any candidate locations for a
1593 trampoline, are within range of the branch. For this reason, the
1594 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1595 relocation in modules at all, and it makes little sense to add
1598 The symptom is that the kernel fails with an "unsupported
1599 relocation" error when loading some modules.
1601 Until fixed tools are available, passing
1602 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1603 code which hits this problem, at the cost of a bit of extra runtime
1604 stack usage in some cases.
1606 The problem is described in more detail at:
1607 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1609 Only Thumb-2 kernels are affected.
1611 Unless you are sure your tools don't have this problem, say Y.
1613 config ARM_ASM_UNIFIED
1617 bool "Use the ARM EABI to compile the kernel"
1619 This option allows for the kernel to be compiled using the latest
1620 ARM ABI (aka EABI). This is only useful if you are using a user
1621 space environment that is also compiled with EABI.
1623 Since there are major incompatibilities between the legacy ABI and
1624 EABI, especially with regard to structure member alignment, this
1625 option also changes the kernel syscall calling convention to
1626 disambiguate both ABIs and allow for backward compatibility support
1627 (selected with CONFIG_OABI_COMPAT).
1629 To use this you need GCC version 4.0.0 or later.
1632 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1633 depends on AEABI && !THUMB2_KERNEL
1635 This option preserves the old syscall interface along with the
1636 new (ARM EABI) one. It also provides a compatibility layer to
1637 intercept syscalls that have structure arguments which layout
1638 in memory differs between the legacy ABI and the new ARM EABI
1639 (only for non "thumb" binaries). This option adds a tiny
1640 overhead to all syscalls and produces a slightly larger kernel.
1642 The seccomp filter system will not be available when this is
1643 selected, since there is no way yet to sensibly distinguish
1644 between calling conventions during filtering.
1646 If you know you'll be using only pure EABI user space then you
1647 can say N here. If this option is not selected and you attempt
1648 to execute a legacy ABI binary then the result will be
1649 UNPREDICTABLE (in fact it can be predicted that it won't work
1650 at all). If in doubt say N.
1652 config ARCH_HAS_HOLES_MEMORYMODEL
1655 config ARCH_SPARSEMEM_ENABLE
1658 config ARCH_SPARSEMEM_DEFAULT
1659 def_bool ARCH_SPARSEMEM_ENABLE
1661 config ARCH_SELECT_MEMORY_MODEL
1662 def_bool ARCH_SPARSEMEM_ENABLE
1664 config HAVE_ARCH_PFN_VALID
1665 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1667 config HAVE_GENERIC_RCU_GUP
1672 bool "High Memory Support"
1675 The address space of ARM processors is only 4 Gigabytes large
1676 and it has to accommodate user address space, kernel address
1677 space as well as some memory mapped IO. That means that, if you
1678 have a large amount of physical memory and/or IO, not all of the
1679 memory can be "permanently mapped" by the kernel. The physical
1680 memory that is not permanently mapped is called "high memory".
1682 Depending on the selected kernel/user memory split, minimum
1683 vmalloc space and actual amount of RAM, you may not need this
1684 option which should result in a slightly faster kernel.
1689 bool "Allocate 2nd-level pagetables from highmem"
1692 config HW_PERF_EVENTS
1693 bool "Enable hardware performance counter support for perf events"
1694 depends on PERF_EVENTS
1697 Enable hardware performance counter support for perf events. If
1698 disabled, perf events will use software events only.
1700 config SYS_SUPPORTS_HUGETLBFS
1704 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1708 config ARCH_WANT_GENERAL_HUGETLB
1713 config FORCE_MAX_ZONEORDER
1714 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1715 range 11 64 if ARCH_SHMOBILE_LEGACY
1716 default "12" if SOC_AM33XX
1717 default "9" if SA1111 || ARCH_EFM32
1720 The kernel memory allocator divides physically contiguous memory
1721 blocks into "zones", where each zone is a power of two number of
1722 pages. This option selects the largest power of two that the kernel
1723 keeps in the memory allocator. If you need to allocate very large
1724 blocks of physically contiguous memory, then you may need to
1725 increase this value.
1727 This config option is actually maximum order plus one. For example,
1728 a value of 11 means that the largest free memory block is 2^10 pages.
1730 config ALIGNMENT_TRAP
1732 depends on CPU_CP15_MMU
1733 default y if !ARCH_EBSA110
1734 select HAVE_PROC_CPU if PROC_FS
1736 ARM processors cannot fetch/store information which is not
1737 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1738 address divisible by 4. On 32-bit ARM processors, these non-aligned
1739 fetch/store instructions will be emulated in software if you say
1740 here, which has a severe performance impact. This is necessary for
1741 correct operation of some network protocols. With an IP-only
1742 configuration it is safe to say N, otherwise say Y.
1744 config UACCESS_WITH_MEMCPY
1745 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1747 default y if CPU_FEROCEON
1749 Implement faster copy_to_user and clear_user methods for CPU
1750 cores where a 8-word STM instruction give significantly higher
1751 memory write throughput than a sequence of individual 32bit stores.
1753 A possible side effect is a slight increase in scheduling latency
1754 between threads sharing the same address space if they invoke
1755 such copy operations with large buffers.
1757 However, if the CPU data cache is using a write-allocate mode,
1758 this option is unlikely to provide any performance gain.
1762 prompt "Enable seccomp to safely compute untrusted bytecode"
1764 This kernel feature is useful for number crunching applications
1765 that may need to compute untrusted bytecode during their
1766 execution. By using pipes or other transports made available to
1767 the process as file descriptors supporting the read/write
1768 syscalls, it's possible to isolate those applications in
1769 their own address space using seccomp. Once seccomp is
1770 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1771 and the task is only allowed to execute a few safe syscalls
1772 defined by each seccomp mode.
1785 bool "Xen guest support on ARM"
1786 depends on ARM && AEABI && OF
1787 depends on CPU_V7 && !CPU_V6
1788 depends on !GENERIC_ATOMIC64
1790 select ARCH_DMA_ADDR_T_64BIT
1794 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1801 bool "Flattened Device Tree support"
1804 select OF_EARLY_FLATTREE
1805 select OF_RESERVED_MEM
1807 Include support for flattened device tree machine descriptions.
1810 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1813 This is the traditional way of passing data to the kernel at boot
1814 time. If you are solely relying on the flattened device tree (or
1815 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1816 to remove ATAGS support from your kernel binary. If unsure,
1819 config DEPRECATED_PARAM_STRUCT
1820 bool "Provide old way to pass kernel parameters"
1823 This was deprecated in 2001 and announced to live on for 5 years.
1824 Some old boot loaders still use this way.
1826 # Compressed boot loader in ROM. Yes, we really want to ask about
1827 # TEXT and BSS so we preserve their values in the config files.
1828 config ZBOOT_ROM_TEXT
1829 hex "Compressed ROM boot loader base address"
1832 The physical address at which the ROM-able zImage is to be
1833 placed in the target. Platforms which normally make use of
1834 ROM-able zImage formats normally set this to a suitable
1835 value in their defconfig file.
1837 If ZBOOT_ROM is not enabled, this has no effect.
1839 config ZBOOT_ROM_BSS
1840 hex "Compressed ROM boot loader BSS address"
1843 The base address of an area of read/write memory in the target
1844 for the ROM-able zImage which must be available while the
1845 decompressor is running. It must be large enough to hold the
1846 entire decompressed kernel plus an additional 128 KiB.
1847 Platforms which normally make use of ROM-able zImage formats
1848 normally set this to a suitable value in their defconfig file.
1850 If ZBOOT_ROM is not enabled, this has no effect.
1853 bool "Compressed boot loader in ROM/flash"
1854 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1855 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1857 Say Y here if you intend to execute your compressed kernel image
1858 (zImage) directly from ROM or flash. If unsure, say N.
1861 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1862 depends on ZBOOT_ROM && ARCH_SH7372
1863 default ZBOOT_ROM_NONE
1865 Include experimental SD/MMC loading code in the ROM-able zImage.
1866 With this enabled it is possible to write the ROM-able zImage
1867 kernel image to an MMC or SD card and boot the kernel straight
1868 from the reset vector. At reset the processor Mask ROM will load
1869 the first part of the ROM-able zImage which in turn loads the
1870 rest the kernel image to RAM.
1872 config ZBOOT_ROM_NONE
1873 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1875 Do not load image from SD or MMC
1877 config ZBOOT_ROM_MMCIF
1878 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1880 Load image from MMCIF hardware block.
1882 config ZBOOT_ROM_SH_MOBILE_SDHI
1883 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1885 Load image from SDHI hardware block
1889 config ARM_APPENDED_DTB
1890 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1893 With this option, the boot code will look for a device tree binary
1894 (DTB) appended to zImage
1895 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1897 This is meant as a backward compatibility convenience for those
1898 systems with a bootloader that can't be upgraded to accommodate
1899 the documented boot protocol using a device tree.
1901 Beware that there is very little in terms of protection against
1902 this option being confused by leftover garbage in memory that might
1903 look like a DTB header after a reboot if no actual DTB is appended
1904 to zImage. Do not leave this option active in a production kernel
1905 if you don't intend to always append a DTB. Proper passing of the
1906 location into r2 of a bootloader provided DTB is always preferable
1909 config ARM_ATAG_DTB_COMPAT
1910 bool "Supplement the appended DTB with traditional ATAG information"
1911 depends on ARM_APPENDED_DTB
1913 Some old bootloaders can't be updated to a DTB capable one, yet
1914 they provide ATAGs with memory configuration, the ramdisk address,
1915 the kernel cmdline string, etc. Such information is dynamically
1916 provided by the bootloader and can't always be stored in a static
1917 DTB. To allow a device tree enabled kernel to be used with such
1918 bootloaders, this option allows zImage to extract the information
1919 from the ATAG list and store it at run time into the appended DTB.
1922 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1923 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1925 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1926 bool "Use bootloader kernel arguments if available"
1928 Uses the command-line options passed by the boot loader instead of
1929 the device tree bootargs property. If the boot loader doesn't provide
1930 any, the device tree bootargs property will be used.
1932 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1933 bool "Extend with bootloader kernel arguments"
1935 The command-line arguments provided by the boot loader will be
1936 appended to the the device tree bootargs property.
1941 string "Default kernel command string"
1944 On some architectures (EBSA110 and CATS), there is currently no way
1945 for the boot loader to pass arguments to the kernel. For these
1946 architectures, you should supply some command-line options at build
1947 time by entering them here. As a minimum, you should specify the
1948 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1951 prompt "Kernel command line type" if CMDLINE != ""
1952 default CMDLINE_FROM_BOOTLOADER
1955 config CMDLINE_FROM_BOOTLOADER
1956 bool "Use bootloader kernel arguments if available"
1958 Uses the command-line options passed by the boot loader. If
1959 the boot loader doesn't provide any, the default kernel command
1960 string provided in CMDLINE will be used.
1962 config CMDLINE_EXTEND
1963 bool "Extend bootloader kernel arguments"
1965 The command-line arguments provided by the boot loader will be
1966 appended to the default kernel command string.
1968 config CMDLINE_FORCE
1969 bool "Always use the default kernel command string"
1971 Always use the default kernel command string, even if the boot
1972 loader passes other arguments to the kernel.
1973 This is useful if you cannot or don't want to change the
1974 command-line options your boot loader passes to the kernel.
1978 bool "Kernel Execute-In-Place from ROM"
1979 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1981 Execute-In-Place allows the kernel to run from non-volatile storage
1982 directly addressable by the CPU, such as NOR flash. This saves RAM
1983 space since the text section of the kernel is not loaded from flash
1984 to RAM. Read-write sections, such as the data section and stack,
1985 are still copied to RAM. The XIP kernel is not compressed since
1986 it has to run directly from flash, so it will take more space to
1987 store it. The flash address used to link the kernel object files,
1988 and for storing it, is configuration dependent. Therefore, if you
1989 say Y here, you must know the proper physical address where to
1990 store the kernel image depending on your own flash memory usage.
1992 Also note that the make target becomes "make xipImage" rather than
1993 "make zImage" or "make Image". The final kernel binary to put in
1994 ROM memory will be arch/arm/boot/xipImage.
1998 config XIP_PHYS_ADDR
1999 hex "XIP Kernel Physical Location"
2000 depends on XIP_KERNEL
2001 default "0x00080000"
2003 This is the physical address in your flash memory the kernel will
2004 be linked for and stored to. This address is dependent on your
2008 bool "Kexec system call (EXPERIMENTAL)"
2009 depends on (!SMP || PM_SLEEP_SMP)
2011 kexec is a system call that implements the ability to shutdown your
2012 current kernel, and to start another kernel. It is like a reboot
2013 but it is independent of the system firmware. And like a reboot
2014 you can start any kernel with it, not just Linux.
2016 It is an ongoing process to be certain the hardware in a machine
2017 is properly shutdown, so do not be surprised if this code does not
2018 initially work for you.
2021 bool "Export atags in procfs"
2022 depends on ATAGS && KEXEC
2025 Should the atags used to boot the kernel be exported in an "atags"
2026 file in procfs. Useful with kexec.
2029 bool "Build kdump crash kernel (EXPERIMENTAL)"
2031 Generate crash dump after being started by kexec. This should
2032 be normally only set in special crash dump kernels which are
2033 loaded in the main kernel with kexec-tools into a specially
2034 reserved region and then later executed after a crash by
2035 kdump/kexec. The crash dump kernel must be compiled to a
2036 memory address not used by the main kernel
2038 For more details see Documentation/kdump/kdump.txt
2040 config AUTO_ZRELADDR
2041 bool "Auto calculation of the decompressed kernel image address"
2043 ZRELADDR is the physical address where the decompressed kernel
2044 image will be placed. If AUTO_ZRELADDR is selected, the address
2045 will be determined at run-time by masking the current IP with
2046 0xf8000000. This assumes the zImage being placed in the first 128MB
2047 from start of memory.
2051 menu "CPU Power Management"
2053 source "drivers/cpufreq/Kconfig"
2055 source "drivers/cpuidle/Kconfig"
2059 menu "Floating point emulation"
2061 comment "At least one emulation must be selected"
2064 bool "NWFPE math emulation"
2065 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2067 Say Y to include the NWFPE floating point emulator in the kernel.
2068 This is necessary to run most binaries. Linux does not currently
2069 support floating point hardware so you need to say Y here even if
2070 your machine has an FPA or floating point co-processor podule.
2072 You may say N here if you are going to load the Acorn FPEmulator
2073 early in the bootup.
2076 bool "Support extended precision"
2077 depends on FPE_NWFPE
2079 Say Y to include 80-bit support in the kernel floating-point
2080 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2081 Note that gcc does not generate 80-bit operations by default,
2082 so in most cases this option only enlarges the size of the
2083 floating point emulator without any good reason.
2085 You almost surely want to say N here.
2088 bool "FastFPE math emulation (EXPERIMENTAL)"
2089 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2091 Say Y here to include the FAST floating point emulator in the kernel.
2092 This is an experimental much faster emulator which now also has full
2093 precision for the mantissa. It does not support any exceptions.
2094 It is very simple, and approximately 3-6 times faster than NWFPE.
2096 It should be sufficient for most programs. It may be not suitable
2097 for scientific calculations, but you have to check this for yourself.
2098 If you do not feel you need a faster FP emulation you should better
2102 bool "VFP-format floating point maths"
2103 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2105 Say Y to include VFP support code in the kernel. This is needed
2106 if your hardware includes a VFP unit.
2108 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2109 release notes and additional status information.
2111 Say N if your target does not have VFP hardware.
2119 bool "Advanced SIMD (NEON) Extension support"
2120 depends on VFPv3 && CPU_V7
2122 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2125 config KERNEL_MODE_NEON
2126 bool "Support for NEON in kernel mode"
2127 depends on NEON && AEABI
2129 Say Y to include support for NEON in kernel mode.
2133 menu "Userspace binary formats"
2135 source "fs/Kconfig.binfmt"
2138 tristate "RISC OS personality"
2141 Say Y here to include the kernel code necessary if you want to run
2142 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2143 experimental; if this sounds frightening, say N and sleep in peace.
2144 You can also say M here to compile this support as a module (which
2145 will be called arthur).
2149 menu "Power management options"
2151 source "kernel/power/Kconfig"
2153 config ARCH_SUSPEND_POSSIBLE
2154 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2155 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2158 config ARM_CPU_SUSPEND
2161 config ARCH_HIBERNATION_POSSIBLE
2164 default y if ARCH_SUSPEND_POSSIBLE
2168 source "net/Kconfig"
2170 source "drivers/Kconfig"
2174 source "arch/arm/Kconfig.debug"
2176 source "security/Kconfig"
2178 source "crypto/Kconfig"
2180 source "lib/Kconfig"
2182 source "arch/arm/kvm/Kconfig"