4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
30 select HAVE_ARCH_TRACEHOOK
32 select HAVE_CONTEXT_TRACKING
33 select HAVE_C_RECORDMCOUNT
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_DEBUG_KMEMLEAK
36 select HAVE_DMA_API_DEBUG
38 select HAVE_DMA_CONTIGUOUS if MMU
39 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
40 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
41 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
42 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
43 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
44 select HAVE_GENERIC_DMA_COHERENT
45 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
46 select HAVE_IDE if PCI || ISA || PCMCIA
47 select HAVE_IRQ_TIME_ACCOUNTING
48 select HAVE_KERNEL_GZIP
49 select HAVE_KERNEL_LZ4
50 select HAVE_KERNEL_LZMA
51 select HAVE_KERNEL_LZO
53 select HAVE_KPROBES if !XIP_KERNEL
54 select HAVE_KRETPROBES if (HAVE_KPROBES)
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
58 select HAVE_PERF_EVENTS
60 select HAVE_PERF_USER_STACK_DUMP
61 select HAVE_REGS_AND_STACK_ACCESS_API
62 select HAVE_SYSCALL_TRACEPOINTS
64 select HAVE_VIRT_CPU_ACCOUNTING_GEN
65 select IRQ_FORCED_THREADING
67 select MODULES_USE_ELF_REL
70 select OLD_SIGSUSPEND3
71 select PERF_USE_VMALLOC
73 select SYS_SUPPORTS_APM_EMULATION
74 # Above selects are sorted alphabetically; please add new ones
75 # according to that. Thanks.
77 The ARM series is a line of low-power-consumption RISC chip designs
78 licensed by ARM Ltd and targeted at embedded applications and
79 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
80 manufactured, but legacy ARM-based PC hardware remains popular in
81 Europe. There is an ARM Linux project with a web page at
82 <http://www.arm.linux.org.uk/>.
84 config ARM_HAS_SG_CHAIN
87 config NEED_SG_DMA_LENGTH
90 config ARM_DMA_USE_IOMMU
92 select ARM_HAS_SG_CHAIN
93 select NEED_SG_DMA_LENGTH
97 config ARM_DMA_IOMMU_ALIGNMENT
98 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
102 DMA mapping framework by default aligns all buffers to the smallest
103 PAGE_SIZE order which is greater than or equal to the requested buffer
104 size. This works well for buffers up to a few hundreds kilobytes, but
105 for larger buffers it just a waste of address space. Drivers which has
106 relatively small addressing window (like 64Mib) might run out of
107 virtual space with just a few allocations.
109 With this parameter you can specify the maximum PAGE_SIZE order for
110 DMA IOMMU buffers. Larger buffers will be aligned only to this
111 specified order. The order is expressed as a power of two multiplied
119 config MIGHT_HAVE_PCI
122 config SYS_SUPPORTS_APM_EMULATION
127 select GENERIC_ALLOCATOR
138 The Extended Industry Standard Architecture (EISA) bus was
139 developed as an open alternative to the IBM MicroChannel bus.
141 The EISA bus provided some of the features of the IBM MicroChannel
142 bus while maintaining backward compatibility with cards made for
143 the older ISA bus. The EISA bus saw limited use between 1988 and
144 1995 when it was made obsolete by the PCI bus.
146 Say Y here if you are building a kernel for an EISA-based machine.
153 config STACKTRACE_SUPPORT
157 config HAVE_LATENCYTOP_SUPPORT
162 config LOCKDEP_SUPPORT
166 config TRACE_IRQFLAGS_SUPPORT
170 config RWSEM_GENERIC_SPINLOCK
174 config RWSEM_XCHGADD_ALGORITHM
177 config ARCH_HAS_ILOG2_U32
180 config ARCH_HAS_ILOG2_U64
183 config ARCH_HAS_CPUFREQ
186 Internal node to signify that the ARCH has CPUFREQ support
187 and that the relevant menu configurations are displayed for
190 config ARCH_HAS_BANDGAP
193 config GENERIC_HWEIGHT
197 config GENERIC_CALIBRATE_DELAY
201 config ARCH_MAY_HAVE_PC_FDC
207 config NEED_DMA_MAP_STATE
210 config ARCH_HAS_DMA_SET_COHERENT_MASK
213 config GENERIC_ISA_DMA
219 config NEED_RET_TO_USER
227 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
228 default DRAM_BASE if REMAP_VECTORS_TO_RAM
231 The base address of exception vectors. This must be two pages
234 config ARM_PATCH_PHYS_VIRT
235 bool "Patch physical to virtual translations at runtime" if EMBEDDED
237 depends on !XIP_KERNEL && MMU
238 depends on !ARCH_REALVIEW || !SPARSEMEM
240 Patch phys-to-virt and virt-to-phys translation functions at
241 boot and module load time according to the position of the
242 kernel in system memory.
244 This can only be used with non-XIP MMU kernels where the base
245 of physical memory is at a 16MB boundary.
247 Only disable this option if you know that you do not require
248 this feature (eg, building a kernel for a single machine) and
249 you need to shrink the kernel to the minimal size.
251 config NEED_MACH_GPIO_H
254 Select this when mach/gpio.h is required to provide special
255 definitions for this platform. The need for mach/gpio.h should
256 be avoided when possible.
258 config NEED_MACH_IO_H
261 Select this when mach/io.h is required to provide special
262 definitions for this platform. The need for mach/io.h should
263 be avoided when possible.
265 config NEED_MACH_MEMORY_H
268 Select this when mach/memory.h is required to provide special
269 definitions for this platform. The need for mach/memory.h should
270 be avoided when possible.
273 hex "Physical address of main memory" if MMU
274 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
275 default DRAM_BASE if !MMU
277 Please provide the physical address corresponding to the
278 location of main memory in your system.
284 source "init/Kconfig"
286 source "kernel/Kconfig.freezer"
291 bool "MMU-based Paged Memory Management Support"
294 Select if you want MMU-based virtualised addressing space
295 support by paged memory management. If unsure, say 'Y'.
298 # The "ARM system type" choice list is ordered alphabetically by option
299 # text. Please add new entries in the option alphabetic order.
302 prompt "ARM system type"
303 default ARCH_VERSATILE if !MMU
304 default ARCH_MULTIPLATFORM if MMU
306 config ARCH_MULTIPLATFORM
307 bool "Allow multiple platforms to be selected"
309 select ARM_PATCH_PHYS_VIRT
312 select MULTI_IRQ_HANDLER
316 config ARCH_INTEGRATOR
317 bool "ARM Ltd. Integrator family"
318 select ARCH_HAS_CPUFREQ
320 select ARM_PATCH_PHYS_VIRT
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
327 select MULTI_IRQ_HANDLER
328 select NEED_MACH_MEMORY_H
329 select PLAT_VERSATILE
332 select VERSATILE_FPGA_IRQ
334 Support for ARM's Integrator platform.
337 bool "ARM Ltd. RealView family"
338 select ARCH_WANT_OPTIONAL_GPIOLIB
340 select ARM_TIMER_SP804
342 select COMMON_CLK_VERSATILE
343 select GENERIC_CLOCKEVENTS
344 select GPIO_PL061 if GPIOLIB
346 select NEED_MACH_MEMORY_H
347 select PLAT_VERSATILE
348 select PLAT_VERSATILE_CLCD
350 This enables support for ARM Ltd RealView boards.
352 config ARCH_VERSATILE
353 bool "ARM Ltd. Versatile family"
354 select ARCH_WANT_OPTIONAL_GPIOLIB
356 select ARM_TIMER_SP804
359 select GENERIC_CLOCKEVENTS
360 select HAVE_MACH_CLKDEV
362 select PLAT_VERSATILE
363 select PLAT_VERSATILE_CLCD
364 select PLAT_VERSATILE_CLOCK
365 select VERSATILE_FPGA_IRQ
367 This enables support for ARM Ltd Versatile board.
371 select ARCH_REQUIRE_GPIOLIB
374 select NEED_MACH_GPIO_H
375 select NEED_MACH_IO_H if PCCARD
377 select PINCTRL_AT91 if USE_OF
379 This enables support for systems based on Atmel
380 AT91RM9200 and AT91SAM9* processors.
383 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
384 select ARCH_REQUIRE_GPIOLIB
389 select GENERIC_CLOCKEVENTS
391 select MULTI_IRQ_HANDLER
394 Support for Cirrus Logic 711x/721x/731x based boards.
397 bool "Cortina Systems Gemini"
398 select ARCH_REQUIRE_GPIOLIB
401 select GENERIC_CLOCKEVENTS
403 Support for the Cortina Systems Gemini family SoCs
407 select ARCH_USES_GETTIMEOFFSET
410 select NEED_MACH_IO_H
411 select NEED_MACH_MEMORY_H
414 This is an evaluation board for the StrongARM processor available
415 from Digital. It has limited hardware on-board, including an
416 Ethernet interface, two PCMCIA sockets, two serial ports and a
420 bool "Energy Micro efm32"
422 select ARCH_REQUIRE_GPIOLIB
424 # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
425 # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
430 select GENERIC_CLOCKEVENTS
436 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
441 select ARCH_HAS_HOLES_MEMORYMODEL
442 select ARCH_REQUIRE_GPIOLIB
443 select ARCH_USES_GETTIMEOFFSET
448 select NEED_MACH_MEMORY_H
450 This enables support for the Cirrus EP93xx series of CPUs.
452 config ARCH_FOOTBRIDGE
456 select GENERIC_CLOCKEVENTS
458 select NEED_MACH_IO_H if !MMU
459 select NEED_MACH_MEMORY_H
461 Support for systems based on the DC21285 companion chip
462 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
465 bool "Hilscher NetX based"
469 select GENERIC_CLOCKEVENTS
471 This enables support for systems based on the Hilscher NetX Soc
477 select NEED_MACH_MEMORY_H
478 select NEED_RET_TO_USER
483 Support for Intel's IOP13XX (XScale) family of processors.
488 select ARCH_REQUIRE_GPIOLIB
491 select NEED_RET_TO_USER
495 Support for Intel's 80219 and IOP32X (XScale) family of
501 select ARCH_REQUIRE_GPIOLIB
504 select NEED_RET_TO_USER
508 Support for Intel's IOP33X (XScale) family of processors.
513 select ARCH_HAS_DMA_SET_COHERENT_MASK
514 select ARCH_SUPPORTS_BIG_ENDIAN
515 select ARCH_REQUIRE_GPIOLIB
518 select DMABOUNCE if PCI
519 select GENERIC_CLOCKEVENTS
520 select MIGHT_HAVE_PCI
521 select NEED_MACH_IO_H
522 select USB_EHCI_BIG_ENDIAN_DESC
523 select USB_EHCI_BIG_ENDIAN_MMIO
525 Support for Intel's IXP4XX (XScale) family of processors.
529 select ARCH_REQUIRE_GPIOLIB
531 select GENERIC_CLOCKEVENTS
532 select MIGHT_HAVE_PCI
536 select PLAT_ORION_LEGACY
538 Support for the Marvell Dove SoC 88AP510
541 bool "Marvell Kirkwood"
542 select ARCH_HAS_CPUFREQ
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
550 select PINCTRL_KIRKWOOD
551 select PLAT_ORION_LEGACY
553 Support for the following Marvell Kirkwood series SoCs:
554 88F6180, 88F6192 and 88F6281.
557 bool "Marvell MV78xx0"
558 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
563 select PLAT_ORION_LEGACY
565 Support for the following Marvell MV78xx0 series SoCs:
571 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_CLOCKEVENTS
576 select PLAT_ORION_LEGACY
578 Support for the following Marvell Orion 5x series SoCs:
579 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
580 Orion-2 (5281), Orion-1-90 (6183).
583 bool "Marvell PXA168/910/MMP2"
585 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_ALLOCATOR
588 select GENERIC_CLOCKEVENTS
591 select MULTI_IRQ_HANDLER
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
599 bool "Micrel/Kendin KS8695"
600 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
604 select NEED_MACH_MEMORY_H
606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607 System-on-Chip devices.
610 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
617 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618 At present, the w90x900 has been renamed nuc900, regarding
619 the ARM series product line, you can login the following
620 link address to know more.
622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
627 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
637 Support for the NXP LPC32XX family of processors
640 bool "PXA2xx/PXA3xx-based"
642 select ARCH_HAS_CPUFREQ
644 select ARCH_REQUIRE_GPIOLIB
645 select ARM_CPU_SUSPEND if PM
649 select GENERIC_CLOCKEVENTS
652 select MULTI_IRQ_HANDLER
656 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
661 select ARCH_REQUIRE_GPIOLIB
663 select GENERIC_CLOCKEVENTS
665 Support for Qualcomm MSM/QSD based systems. This runs on the
666 apps processor of the MSM/QSD and depends on a shared memory
667 interface to the modem processor which runs the baseband
668 stack and controls some vital subsystems
669 (clock and power control, etc).
671 config ARCH_SHMOBILE_LEGACY
672 bool "Renesas ARM SoCs (non-multiplatform)"
674 select ARM_PATCH_PHYS_VIRT
676 select GENERIC_CLOCKEVENTS
677 select HAVE_ARM_SCU if SMP
678 select HAVE_ARM_TWD if SMP
679 select HAVE_MACH_CLKDEV
681 select MIGHT_HAVE_CACHE_L2X0
682 select MULTI_IRQ_HANDLER
685 select PM_GENERIC_DOMAINS if PM
688 Support for Renesas ARM SoC platforms using a non-multiplatform
689 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
695 select ARCH_MAY_HAVE_PC_FDC
696 select ARCH_SPARSEMEM_ENABLE
697 select ARCH_USES_GETTIMEOFFSET
700 select HAVE_PATA_PLATFORM
702 select NEED_MACH_IO_H
703 select NEED_MACH_MEMORY_H
707 On the Acorn Risc-PC, Linux can support the internal IDE disk and
708 CD-ROM interface, serial and parallel port, and the floppy drive.
712 select ARCH_HAS_CPUFREQ
714 select ARCH_REQUIRE_GPIOLIB
715 select ARCH_SPARSEMEM_ENABLE
720 select GENERIC_CLOCKEVENTS
723 select NEED_MACH_MEMORY_H
726 Support for StrongARM 11x0 based boards.
729 bool "Samsung S3C24XX SoCs"
730 select ARCH_HAS_CPUFREQ
731 select ARCH_REQUIRE_GPIOLIB
733 select CLKSRC_SAMSUNG_PWM
734 select GENERIC_CLOCKEVENTS
736 select HAVE_S3C2410_I2C if I2C
737 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 select HAVE_S3C_RTC if RTC_CLASS
739 select MULTI_IRQ_HANDLER
740 select NEED_MACH_IO_H
743 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
744 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
745 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
746 Samsung SMDK2410 development board (and derivatives).
749 bool "Samsung S3C64XX"
750 select ARCH_HAS_CPUFREQ
751 select ARCH_REQUIRE_GPIOLIB
755 select CLKSRC_SAMSUNG_PWM
758 select GENERIC_CLOCKEVENTS
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 select PM_GENERIC_DOMAINS
767 select S3C_GPIO_TRACK
769 select SAMSUNG_WAKEMASK
770 select SAMSUNG_WDT_RESET
772 Samsung S3C64XX series based systems
775 bool "Samsung S5P6440 S5P6450"
777 select CLKSRC_SAMSUNG_PWM
779 select GENERIC_CLOCKEVENTS
781 select HAVE_S3C2410_I2C if I2C
782 select HAVE_S3C2410_WATCHDOG if WATCHDOG
783 select HAVE_S3C_RTC if RTC_CLASS
784 select NEED_MACH_GPIO_H
786 select SAMSUNG_WDT_RESET
788 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
792 bool "Samsung S5PC100"
793 select ARCH_REQUIRE_GPIOLIB
795 select CLKSRC_SAMSUNG_PWM
797 select GENERIC_CLOCKEVENTS
799 select HAVE_S3C2410_I2C if I2C
800 select HAVE_S3C2410_WATCHDOG if WATCHDOG
801 select HAVE_S3C_RTC if RTC_CLASS
802 select NEED_MACH_GPIO_H
804 select SAMSUNG_WDT_RESET
806 Samsung S5PC100 series based systems
809 bool "Samsung S5PV210/S5PC110"
810 select ARCH_HAS_CPUFREQ
811 select ARCH_HAS_HOLES_MEMORYMODEL
812 select ARCH_SPARSEMEM_ENABLE
814 select CLKSRC_SAMSUNG_PWM
816 select GENERIC_CLOCKEVENTS
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 select HAVE_S3C_RTC if RTC_CLASS
821 select NEED_MACH_GPIO_H
822 select NEED_MACH_MEMORY_H
825 Samsung S5PV210/S5PC110 series based systems
828 bool "Samsung EXYNOS"
829 select ARCH_HAS_CPUFREQ
830 select ARCH_HAS_HOLES_MEMORYMODEL
831 select ARCH_REQUIRE_GPIOLIB
832 select ARCH_SPARSEMEM_ENABLE
836 select GENERIC_CLOCKEVENTS
837 select HAVE_S3C2410_I2C if I2C
838 select HAVE_S3C2410_WATCHDOG if WATCHDOG
839 select HAVE_S3C_RTC if RTC_CLASS
840 select NEED_MACH_MEMORY_H
844 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
848 select ARCH_HAS_HOLES_MEMORYMODEL
849 select ARCH_REQUIRE_GPIOLIB
851 select GENERIC_ALLOCATOR
852 select GENERIC_CLOCKEVENTS
853 select GENERIC_IRQ_CHIP
859 Support for TI's DaVinci platform.
864 select ARCH_HAS_CPUFREQ
865 select ARCH_HAS_HOLES_MEMORYMODEL
867 select ARCH_REQUIRE_GPIOLIB
870 select GENERIC_CLOCKEVENTS
871 select GENERIC_IRQ_CHIP
874 select NEED_MACH_IO_H if PCCARD
875 select NEED_MACH_MEMORY_H
877 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
881 menu "Multiple platform selection"
882 depends on ARCH_MULTIPLATFORM
884 comment "CPU Core family selection"
886 config ARCH_MULTI_V4T
887 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
888 depends on !ARCH_MULTI_V6_V7
889 select ARCH_MULTI_V4_V5
890 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
891 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
892 CPU_ARM925T || CPU_ARM940T)
895 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
896 depends on !ARCH_MULTI_V6_V7
897 select ARCH_MULTI_V4_V5
898 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
899 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
900 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
902 config ARCH_MULTI_V4_V5
906 bool "ARMv6 based platforms (ARM11)"
907 select ARCH_MULTI_V6_V7
911 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
913 select ARCH_MULTI_V6_V7
916 config ARCH_MULTI_V6_V7
919 config ARCH_MULTI_CPU_AUTO
920 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
926 # This is sorted alphabetically by mach-* pathname. However, plat-*
927 # Kconfigs may be included either alphabetically (according to the
928 # plat- suffix) or along side the corresponding mach-* source.
930 source "arch/arm/mach-mvebu/Kconfig"
932 source "arch/arm/mach-at91/Kconfig"
934 source "arch/arm/mach-bcm/Kconfig"
936 source "arch/arm/mach-bcm2835/Kconfig"
938 source "arch/arm/mach-berlin/Kconfig"
940 source "arch/arm/mach-clps711x/Kconfig"
942 source "arch/arm/mach-cns3xxx/Kconfig"
944 source "arch/arm/mach-davinci/Kconfig"
946 source "arch/arm/mach-dove/Kconfig"
948 source "arch/arm/mach-ep93xx/Kconfig"
950 source "arch/arm/mach-footbridge/Kconfig"
952 source "arch/arm/mach-gemini/Kconfig"
954 source "arch/arm/mach-highbank/Kconfig"
956 source "arch/arm/mach-hisi/Kconfig"
958 source "arch/arm/mach-integrator/Kconfig"
960 source "arch/arm/mach-iop32x/Kconfig"
962 source "arch/arm/mach-iop33x/Kconfig"
964 source "arch/arm/mach-iop13xx/Kconfig"
966 source "arch/arm/mach-ixp4xx/Kconfig"
968 source "arch/arm/mach-keystone/Kconfig"
970 source "arch/arm/mach-kirkwood/Kconfig"
972 source "arch/arm/mach-ks8695/Kconfig"
974 source "arch/arm/mach-msm/Kconfig"
976 source "arch/arm/mach-moxart/Kconfig"
978 source "arch/arm/mach-mv78xx0/Kconfig"
980 source "arch/arm/mach-imx/Kconfig"
982 source "arch/arm/mach-mxs/Kconfig"
984 source "arch/arm/mach-netx/Kconfig"
986 source "arch/arm/mach-nomadik/Kconfig"
988 source "arch/arm/mach-nspire/Kconfig"
990 source "arch/arm/plat-omap/Kconfig"
992 source "arch/arm/mach-omap1/Kconfig"
994 source "arch/arm/mach-omap2/Kconfig"
996 source "arch/arm/mach-orion5x/Kconfig"
998 source "arch/arm/mach-picoxcell/Kconfig"
1000 source "arch/arm/mach-pxa/Kconfig"
1001 source "arch/arm/plat-pxa/Kconfig"
1003 source "arch/arm/mach-mmp/Kconfig"
1005 source "arch/arm/mach-realview/Kconfig"
1007 source "arch/arm/mach-rockchip/Kconfig"
1009 source "arch/arm/mach-sa1100/Kconfig"
1011 source "arch/arm/plat-samsung/Kconfig"
1013 source "arch/arm/mach-socfpga/Kconfig"
1015 source "arch/arm/mach-spear/Kconfig"
1017 source "arch/arm/mach-sti/Kconfig"
1019 source "arch/arm/mach-s3c24xx/Kconfig"
1021 source "arch/arm/mach-s3c64xx/Kconfig"
1023 source "arch/arm/mach-s5p64x0/Kconfig"
1025 source "arch/arm/mach-s5pc100/Kconfig"
1027 source "arch/arm/mach-s5pv210/Kconfig"
1029 source "arch/arm/mach-exynos/Kconfig"
1031 source "arch/arm/mach-shmobile/Kconfig"
1033 source "arch/arm/mach-sunxi/Kconfig"
1035 source "arch/arm/mach-prima2/Kconfig"
1037 source "arch/arm/mach-tegra/Kconfig"
1039 source "arch/arm/mach-u300/Kconfig"
1041 source "arch/arm/mach-ux500/Kconfig"
1043 source "arch/arm/mach-versatile/Kconfig"
1045 source "arch/arm/mach-vexpress/Kconfig"
1046 source "arch/arm/plat-versatile/Kconfig"
1048 source "arch/arm/mach-virt/Kconfig"
1050 source "arch/arm/mach-vt8500/Kconfig"
1052 source "arch/arm/mach-w90x900/Kconfig"
1054 source "arch/arm/mach-zynq/Kconfig"
1056 # Definitions to make life easier
1062 select GENERIC_CLOCKEVENTS
1068 select GENERIC_IRQ_CHIP
1071 config PLAT_ORION_LEGACY
1078 config PLAT_VERSATILE
1081 config ARM_TIMER_SP804
1084 select CLKSRC_OF if OF
1086 source "arch/arm/firmware/Kconfig"
1088 source arch/arm/mm/Kconfig
1092 default 16 if ARCH_EP93XX
1096 bool "Enable iWMMXt support" if !CPU_PJ4
1097 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1098 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1100 Enable support for iWMMXt context switching at run time if
1101 running on a CPU that supports it.
1103 config MULTI_IRQ_HANDLER
1106 Allow each machine to specify it's own IRQ handler at run time.
1109 source "arch/arm/Kconfig-nommu"
1112 config PJ4B_ERRATA_4742
1113 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1114 depends on CPU_PJ4B && MACH_ARMADA_370
1117 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1118 Event (WFE) IDLE states, a specific timing sensitivity exists between
1119 the retiring WFI/WFE instructions and the newly issued subsequent
1120 instructions. This sensitivity can result in a CPU hang scenario.
1122 The software must insert either a Data Synchronization Barrier (DSB)
1123 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1126 config ARM_ERRATA_326103
1127 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1130 Executing a SWP instruction to read-only memory does not set bit 11
1131 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1132 treat the access as a read, preventing a COW from occurring and
1133 causing the faulting task to livelock.
1135 config ARM_ERRATA_411920
1136 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1137 depends on CPU_V6 || CPU_V6K
1139 Invalidation of the Instruction Cache operation can
1140 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1141 It does not affect the MPCore. This option enables the ARM Ltd.
1142 recommended workaround.
1144 config ARM_ERRATA_430973
1145 bool "ARM errata: Stale prediction on replaced interworking branch"
1148 This option enables the workaround for the 430973 Cortex-A8
1149 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1150 interworking branch is replaced with another code sequence at the
1151 same virtual address, whether due to self-modifying code or virtual
1152 to physical address re-mapping, Cortex-A8 does not recover from the
1153 stale interworking branch prediction. This results in Cortex-A8
1154 executing the new code sequence in the incorrect ARM or Thumb state.
1155 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1156 and also flushes the branch target cache at every context switch.
1157 Note that setting specific bits in the ACTLR register may not be
1158 available in non-secure mode.
1160 config ARM_ERRATA_458693
1161 bool "ARM errata: Processor deadlock when a false hazard is created"
1163 depends on !ARCH_MULTIPLATFORM
1165 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1166 erratum. For very specific sequences of memory operations, it is
1167 possible for a hazard condition intended for a cache line to instead
1168 be incorrectly associated with a different cache line. This false
1169 hazard might then cause a processor deadlock. The workaround enables
1170 the L1 caching of the NEON accesses and disables the PLD instruction
1171 in the ACTLR register. Note that setting specific bits in the ACTLR
1172 register may not be available in non-secure mode.
1174 config ARM_ERRATA_460075
1175 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1177 depends on !ARCH_MULTIPLATFORM
1179 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1180 erratum. Any asynchronous access to the L2 cache may encounter a
1181 situation in which recent store transactions to the L2 cache are lost
1182 and overwritten with stale memory contents from external memory. The
1183 workaround disables the write-allocate mode for the L2 cache via the
1184 ACTLR register. Note that setting specific bits in the ACTLR register
1185 may not be available in non-secure mode.
1187 config ARM_ERRATA_742230
1188 bool "ARM errata: DMB operation may be faulty"
1189 depends on CPU_V7 && SMP
1190 depends on !ARCH_MULTIPLATFORM
1192 This option enables the workaround for the 742230 Cortex-A9
1193 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1194 between two write operations may not ensure the correct visibility
1195 ordering of the two writes. This workaround sets a specific bit in
1196 the diagnostic register of the Cortex-A9 which causes the DMB
1197 instruction to behave as a DSB, ensuring the correct behaviour of
1200 config ARM_ERRATA_742231
1201 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1202 depends on CPU_V7 && SMP
1203 depends on !ARCH_MULTIPLATFORM
1205 This option enables the workaround for the 742231 Cortex-A9
1206 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1207 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1208 accessing some data located in the same cache line, may get corrupted
1209 data due to bad handling of the address hazard when the line gets
1210 replaced from one of the CPUs at the same time as another CPU is
1211 accessing it. This workaround sets specific bits in the diagnostic
1212 register of the Cortex-A9 which reduces the linefill issuing
1213 capabilities of the processor.
1215 config PL310_ERRATA_588369
1216 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1217 depends on CACHE_L2X0
1219 The PL310 L2 cache controller implements three types of Clean &
1220 Invalidate maintenance operations: by Physical Address
1221 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1222 They are architecturally defined to behave as the execution of a
1223 clean operation followed immediately by an invalidate operation,
1224 both performing to the same memory location. This functionality
1225 is not correctly implemented in PL310 as clean lines are not
1226 invalidated as a result of these operations.
1228 config ARM_ERRATA_643719
1229 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1230 depends on CPU_V7 && SMP
1232 This option enables the workaround for the 643719 Cortex-A9 (prior to
1233 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1234 register returns zero when it should return one. The workaround
1235 corrects this value, ensuring cache maintenance operations which use
1236 it behave as intended and avoiding data corruption.
1238 config ARM_ERRATA_720789
1239 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1242 This option enables the workaround for the 720789 Cortex-A9 (prior to
1243 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1244 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1245 As a consequence of this erratum, some TLB entries which should be
1246 invalidated are not, resulting in an incoherency in the system page
1247 tables. The workaround changes the TLB flushing routines to invalidate
1248 entries regardless of the ASID.
1250 config PL310_ERRATA_727915
1251 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1252 depends on CACHE_L2X0
1254 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1255 operation (offset 0x7FC). This operation runs in background so that
1256 PL310 can handle normal accesses while it is in progress. Under very
1257 rare circumstances, due to this erratum, write data can be lost when
1258 PL310 treats a cacheable write transaction during a Clean &
1259 Invalidate by Way operation.
1261 config ARM_ERRATA_743622
1262 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1264 depends on !ARCH_MULTIPLATFORM
1266 This option enables the workaround for the 743622 Cortex-A9
1267 (r2p*) erratum. Under very rare conditions, a faulty
1268 optimisation in the Cortex-A9 Store Buffer may lead to data
1269 corruption. This workaround sets a specific bit in the diagnostic
1270 register of the Cortex-A9 which disables the Store Buffer
1271 optimisation, preventing the defect from occurring. This has no
1272 visible impact on the overall performance or power consumption of the
1275 config ARM_ERRATA_751472
1276 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1278 depends on !ARCH_MULTIPLATFORM
1280 This option enables the workaround for the 751472 Cortex-A9 (prior
1281 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1282 completion of a following broadcasted operation if the second
1283 operation is received by a CPU before the ICIALLUIS has completed,
1284 potentially leading to corrupted entries in the cache or TLB.
1286 config PL310_ERRATA_753970
1287 bool "PL310 errata: cache sync operation may be faulty"
1288 depends on CACHE_PL310
1290 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1292 Under some condition the effect of cache sync operation on
1293 the store buffer still remains when the operation completes.
1294 This means that the store buffer is always asked to drain and
1295 this prevents it from merging any further writes. The workaround
1296 is to replace the normal offset of cache sync operation (0x730)
1297 by another offset targeting an unmapped PL310 register 0x740.
1298 This has the same effect as the cache sync operation: store buffer
1299 drain and waiting for all buffers empty.
1301 config ARM_ERRATA_754322
1302 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1305 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1306 r3p*) erratum. A speculative memory access may cause a page table walk
1307 which starts prior to an ASID switch but completes afterwards. This
1308 can populate the micro-TLB with a stale entry which may be hit with
1309 the new ASID. This workaround places two dsb instructions in the mm
1310 switching code so that no page table walks can cross the ASID switch.
1312 config ARM_ERRATA_754327
1313 bool "ARM errata: no automatic Store Buffer drain"
1314 depends on CPU_V7 && SMP
1316 This option enables the workaround for the 754327 Cortex-A9 (prior to
1317 r2p0) erratum. The Store Buffer does not have any automatic draining
1318 mechanism and therefore a livelock may occur if an external agent
1319 continuously polls a memory location waiting to observe an update.
1320 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1321 written polling loops from denying visibility of updates to memory.
1323 config ARM_ERRATA_364296
1324 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1327 This options enables the workaround for the 364296 ARM1136
1328 r0p2 erratum (possible cache data corruption with
1329 hit-under-miss enabled). It sets the undocumented bit 31 in
1330 the auxiliary control register and the FI bit in the control
1331 register, thus disabling hit-under-miss without putting the
1332 processor into full low interrupt latency mode. ARM11MPCore
1335 config ARM_ERRATA_764369
1336 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1337 depends on CPU_V7 && SMP
1339 This option enables the workaround for erratum 764369
1340 affecting Cortex-A9 MPCore with two or more processors (all
1341 current revisions). Under certain timing circumstances, a data
1342 cache line maintenance operation by MVA targeting an Inner
1343 Shareable memory region may fail to proceed up to either the
1344 Point of Coherency or to the Point of Unification of the
1345 system. This workaround adds a DSB instruction before the
1346 relevant cache maintenance functions and sets a specific bit
1347 in the diagnostic control register of the SCU.
1349 config PL310_ERRATA_769419
1350 bool "PL310 errata: no automatic Store Buffer drain"
1351 depends on CACHE_L2X0
1353 On revisions of the PL310 prior to r3p2, the Store Buffer does
1354 not automatically drain. This can cause normal, non-cacheable
1355 writes to be retained when the memory system is idle, leading
1356 to suboptimal I/O performance for drivers using coherent DMA.
1357 This option adds a write barrier to the cpu_idle loop so that,
1358 on systems with an outer cache, the store buffer is drained
1361 config ARM_ERRATA_775420
1362 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1365 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1366 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1367 operation aborts with MMU exception, it might cause the processor
1368 to deadlock. This workaround puts DSB before executing ISB if
1369 an abort may occur on cache maintenance.
1371 config ARM_ERRATA_798181
1372 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1373 depends on CPU_V7 && SMP
1375 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1376 adequately shooting down all use of the old entries. This
1377 option enables the Linux kernel workaround for this erratum
1378 which sends an IPI to the CPUs that are running the same ASID
1379 as the one being invalidated.
1381 config ARM_ERRATA_773022
1382 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1385 This option enables the workaround for the 773022 Cortex-A15
1386 (up to r0p4) erratum. In certain rare sequences of code, the
1387 loop buffer may deliver incorrect instructions. This
1388 workaround disables the loop buffer to avoid the erratum.
1392 source "arch/arm/common/Kconfig"
1402 Find out whether you have ISA slots on your motherboard. ISA is the
1403 name of a bus system, i.e. the way the CPU talks to the other stuff
1404 inside your box. Other bus systems are PCI, EISA, MicroChannel
1405 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1406 newer boards don't support it. If you have ISA, say Y, otherwise N.
1408 # Select ISA DMA controller support
1413 # Select ISA DMA interface
1418 bool "PCI support" if MIGHT_HAVE_PCI
1420 Find out whether you have a PCI motherboard. PCI is the name of a
1421 bus system, i.e. the way the CPU talks to the other stuff inside
1422 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1423 VESA. If you have PCI, say Y, otherwise N.
1429 config PCI_NANOENGINE
1430 bool "BSE nanoEngine PCI support"
1431 depends on SA1100_NANOENGINE
1433 Enable PCI on the BSE nanoEngine board.
1438 config PCI_HOST_ITE8152
1440 depends on PCI && MACH_ARMCORE
1444 source "drivers/pci/Kconfig"
1445 source "drivers/pci/pcie/Kconfig"
1447 source "drivers/pcmcia/Kconfig"
1451 menu "Kernel Features"
1456 This option should be selected by machines which have an SMP-
1459 The only effect of this option is to make the SMP-related
1460 options available to the user for configuration.
1463 bool "Symmetric Multi-Processing"
1464 depends on CPU_V6K || CPU_V7
1465 depends on GENERIC_CLOCKEVENTS
1467 depends on MMU || ARM_MPU
1469 This enables support for systems with more than one CPU. If you have
1470 a system with only one CPU, say N. If you have a system with more
1471 than one CPU, say Y.
1473 If you say N here, the kernel will run on uni- and multiprocessor
1474 machines, but will use only one CPU of a multiprocessor machine. If
1475 you say Y here, the kernel will run on many, but not all,
1476 uniprocessor machines. On a uniprocessor machine, the kernel
1477 will run faster if you say N here.
1479 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1480 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1481 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1483 If you don't know what to do here, say N.
1486 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1487 depends on SMP && !XIP_KERNEL && MMU
1490 SMP kernels contain instructions which fail on non-SMP processors.
1491 Enabling this option allows the kernel to modify itself to make
1492 these instructions safe. Disabling it allows about 1K of space
1495 If you don't know what to do here, say Y.
1497 config ARM_CPU_TOPOLOGY
1498 bool "Support cpu topology definition"
1499 depends on SMP && CPU_V7
1502 Support ARM cpu topology definition. The MPIDR register defines
1503 affinity between processors which is then used to describe the cpu
1504 topology of an ARM System.
1507 bool "Multi-core scheduler support"
1508 depends on ARM_CPU_TOPOLOGY
1510 Multi-core scheduler support improves the CPU scheduler's decision
1511 making when dealing with multi-core CPU chips at a cost of slightly
1512 increased overhead in some places. If unsure say N here.
1515 bool "SMT scheduler support"
1516 depends on ARM_CPU_TOPOLOGY
1518 Improves the CPU scheduler's decision making when dealing with
1519 MultiThreading at a cost of slightly increased overhead in some
1520 places. If unsure say N here.
1525 This option enables support for the ARM system coherency unit
1527 config HAVE_ARM_ARCH_TIMER
1528 bool "Architected timer support"
1530 select ARM_ARCH_TIMER
1531 select GENERIC_CLOCKEVENTS
1533 This option enables support for the ARM architected timer
1538 select CLKSRC_OF if OF
1540 This options enables support for the ARM timer and watchdog unit
1543 bool "Multi-Cluster Power Management"
1544 depends on CPU_V7 && SMP
1546 This option provides the common power management infrastructure
1547 for (multi-)cluster based systems, such as big.LITTLE based
1551 bool "big.LITTLE support (Experimental)"
1552 depends on CPU_V7 && SMP
1555 This option enables support selections for the big.LITTLE
1556 system architecture.
1559 bool "big.LITTLE switcher support"
1560 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1562 select ARM_CPU_SUSPEND
1564 The big.LITTLE "switcher" provides the core functionality to
1565 transparently handle transition between a cluster of A15's
1566 and a cluster of A7's in a big.LITTLE system.
1568 config BL_SWITCHER_DUMMY_IF
1569 tristate "Simple big.LITTLE switcher user interface"
1570 depends on BL_SWITCHER && DEBUG_KERNEL
1572 This is a simple and dummy char dev interface to control
1573 the big.LITTLE switcher core code. It is meant for
1574 debugging purposes only.
1577 prompt "Memory split"
1581 Select the desired split between kernel and user memory.
1583 If you are not absolutely sure what you are doing, leave this
1587 bool "3G/1G user/kernel split"
1589 bool "2G/2G user/kernel split"
1591 bool "1G/3G user/kernel split"
1596 default PHYS_OFFSET if !MMU
1597 default 0x40000000 if VMSPLIT_1G
1598 default 0x80000000 if VMSPLIT_2G
1602 int "Maximum number of CPUs (2-32)"
1608 bool "Support for hot-pluggable CPUs"
1611 Say Y here to experiment with turning CPUs off and on. CPUs
1612 can be controlled through /sys/devices/system/cpu.
1615 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1618 Say Y here if you want Linux to communicate with system firmware
1619 implementing the PSCI specification for CPU-centric power
1620 management operations described in ARM document number ARM DEN
1621 0022A ("Power State Coordination Interface System Software on
1624 # The GPIO number here must be sorted by descending number. In case of
1625 # a multiplatform kernel, we just want the highest value required by the
1626 # selected platforms.
1629 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1630 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1631 default 392 if ARCH_U8500
1632 default 352 if ARCH_VT8500
1633 default 288 if ARCH_SUNXI
1634 default 264 if MACH_H4700
1637 Maximum number of GPIOs in the system.
1639 If unsure, leave the default value.
1641 source kernel/Kconfig.preempt
1645 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1646 ARCH_S5PV210 || ARCH_EXYNOS4
1647 default AT91_TIMER_HZ if ARCH_AT91
1648 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1652 depends on HZ_FIXED = 0
1653 prompt "Timer frequency"
1677 default HZ_FIXED if HZ_FIXED != 0
1678 default 100 if HZ_100
1679 default 200 if HZ_200
1680 default 250 if HZ_250
1681 default 300 if HZ_300
1682 default 500 if HZ_500
1686 def_bool HIGH_RES_TIMERS
1688 config THUMB2_KERNEL
1689 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1690 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1691 default y if CPU_THUMBONLY
1693 select ARM_ASM_UNIFIED
1696 By enabling this option, the kernel will be compiled in
1697 Thumb-2 mode. A compiler/assembler that understand the unified
1698 ARM-Thumb syntax is needed.
1702 config THUMB2_AVOID_R_ARM_THM_JUMP11
1703 bool "Work around buggy Thumb-2 short branch relocations in gas"
1704 depends on THUMB2_KERNEL && MODULES
1707 Various binutils versions can resolve Thumb-2 branches to
1708 locally-defined, preemptible global symbols as short-range "b.n"
1709 branch instructions.
1711 This is a problem, because there's no guarantee the final
1712 destination of the symbol, or any candidate locations for a
1713 trampoline, are within range of the branch. For this reason, the
1714 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1715 relocation in modules at all, and it makes little sense to add
1718 The symptom is that the kernel fails with an "unsupported
1719 relocation" error when loading some modules.
1721 Until fixed tools are available, passing
1722 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1723 code which hits this problem, at the cost of a bit of extra runtime
1724 stack usage in some cases.
1726 The problem is described in more detail at:
1727 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1729 Only Thumb-2 kernels are affected.
1731 Unless you are sure your tools don't have this problem, say Y.
1733 config ARM_ASM_UNIFIED
1737 bool "Use the ARM EABI to compile the kernel"
1739 This option allows for the kernel to be compiled using the latest
1740 ARM ABI (aka EABI). This is only useful if you are using a user
1741 space environment that is also compiled with EABI.
1743 Since there are major incompatibilities between the legacy ABI and
1744 EABI, especially with regard to structure member alignment, this
1745 option also changes the kernel syscall calling convention to
1746 disambiguate both ABIs and allow for backward compatibility support
1747 (selected with CONFIG_OABI_COMPAT).
1749 To use this you need GCC version 4.0.0 or later.
1752 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1753 depends on AEABI && !THUMB2_KERNEL
1755 This option preserves the old syscall interface along with the
1756 new (ARM EABI) one. It also provides a compatibility layer to
1757 intercept syscalls that have structure arguments which layout
1758 in memory differs between the legacy ABI and the new ARM EABI
1759 (only for non "thumb" binaries). This option adds a tiny
1760 overhead to all syscalls and produces a slightly larger kernel.
1762 The seccomp filter system will not be available when this is
1763 selected, since there is no way yet to sensibly distinguish
1764 between calling conventions during filtering.
1766 If you know you'll be using only pure EABI user space then you
1767 can say N here. If this option is not selected and you attempt
1768 to execute a legacy ABI binary then the result will be
1769 UNPREDICTABLE (in fact it can be predicted that it won't work
1770 at all). If in doubt say N.
1772 config ARCH_HAS_HOLES_MEMORYMODEL
1775 config ARCH_SPARSEMEM_ENABLE
1778 config ARCH_SPARSEMEM_DEFAULT
1779 def_bool ARCH_SPARSEMEM_ENABLE
1781 config ARCH_SELECT_MEMORY_MODEL
1782 def_bool ARCH_SPARSEMEM_ENABLE
1784 config HAVE_ARCH_PFN_VALID
1785 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1788 bool "High Memory Support"
1791 The address space of ARM processors is only 4 Gigabytes large
1792 and it has to accommodate user address space, kernel address
1793 space as well as some memory mapped IO. That means that, if you
1794 have a large amount of physical memory and/or IO, not all of the
1795 memory can be "permanently mapped" by the kernel. The physical
1796 memory that is not permanently mapped is called "high memory".
1798 Depending on the selected kernel/user memory split, minimum
1799 vmalloc space and actual amount of RAM, you may not need this
1800 option which should result in a slightly faster kernel.
1805 bool "Allocate 2nd-level pagetables from highmem"
1808 config HW_PERF_EVENTS
1809 bool "Enable hardware performance counter support for perf events"
1810 depends on PERF_EVENTS
1813 Enable hardware performance counter support for perf events. If
1814 disabled, perf events will use software events only.
1816 config SYS_SUPPORTS_HUGETLBFS
1820 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1824 config ARCH_WANT_GENERAL_HUGETLB
1829 config FORCE_MAX_ZONEORDER
1830 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1831 range 11 64 if ARCH_SHMOBILE_LEGACY
1832 default "12" if SOC_AM33XX
1833 default "9" if SA1111 || ARCH_EFM32
1836 The kernel memory allocator divides physically contiguous memory
1837 blocks into "zones", where each zone is a power of two number of
1838 pages. This option selects the largest power of two that the kernel
1839 keeps in the memory allocator. If you need to allocate very large
1840 blocks of physically contiguous memory, then you may need to
1841 increase this value.
1843 This config option is actually maximum order plus one. For example,
1844 a value of 11 means that the largest free memory block is 2^10 pages.
1846 config ALIGNMENT_TRAP
1848 depends on CPU_CP15_MMU
1849 default y if !ARCH_EBSA110
1850 select HAVE_PROC_CPU if PROC_FS
1852 ARM processors cannot fetch/store information which is not
1853 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1854 address divisible by 4. On 32-bit ARM processors, these non-aligned
1855 fetch/store instructions will be emulated in software if you say
1856 here, which has a severe performance impact. This is necessary for
1857 correct operation of some network protocols. With an IP-only
1858 configuration it is safe to say N, otherwise say Y.
1860 config UACCESS_WITH_MEMCPY
1861 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1863 default y if CPU_FEROCEON
1865 Implement faster copy_to_user and clear_user methods for CPU
1866 cores where a 8-word STM instruction give significantly higher
1867 memory write throughput than a sequence of individual 32bit stores.
1869 A possible side effect is a slight increase in scheduling latency
1870 between threads sharing the same address space if they invoke
1871 such copy operations with large buffers.
1873 However, if the CPU data cache is using a write-allocate mode,
1874 this option is unlikely to provide any performance gain.
1878 prompt "Enable seccomp to safely compute untrusted bytecode"
1880 This kernel feature is useful for number crunching applications
1881 that may need to compute untrusted bytecode during their
1882 execution. By using pipes or other transports made available to
1883 the process as file descriptors supporting the read/write
1884 syscalls, it's possible to isolate those applications in
1885 their own address space using seccomp. Once seccomp is
1886 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1887 and the task is only allowed to execute a few safe syscalls
1888 defined by each seccomp mode.
1901 bool "Xen guest support on ARM (EXPERIMENTAL)"
1902 depends on ARM && AEABI && OF
1903 depends on CPU_V7 && !CPU_V6
1904 depends on !GENERIC_ATOMIC64
1908 select ARCH_DMA_ADDR_T_64BIT
1910 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1917 bool "Flattened Device Tree support"
1920 select OF_EARLY_FLATTREE
1921 select OF_RESERVED_MEM
1923 Include support for flattened device tree machine descriptions.
1926 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1929 This is the traditional way of passing data to the kernel at boot
1930 time. If you are solely relying on the flattened device tree (or
1931 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1932 to remove ATAGS support from your kernel binary. If unsure,
1935 config DEPRECATED_PARAM_STRUCT
1936 bool "Provide old way to pass kernel parameters"
1939 This was deprecated in 2001 and announced to live on for 5 years.
1940 Some old boot loaders still use this way.
1942 # Compressed boot loader in ROM. Yes, we really want to ask about
1943 # TEXT and BSS so we preserve their values in the config files.
1944 config ZBOOT_ROM_TEXT
1945 hex "Compressed ROM boot loader base address"
1948 The physical address at which the ROM-able zImage is to be
1949 placed in the target. Platforms which normally make use of
1950 ROM-able zImage formats normally set this to a suitable
1951 value in their defconfig file.
1953 If ZBOOT_ROM is not enabled, this has no effect.
1955 config ZBOOT_ROM_BSS
1956 hex "Compressed ROM boot loader BSS address"
1959 The base address of an area of read/write memory in the target
1960 for the ROM-able zImage which must be available while the
1961 decompressor is running. It must be large enough to hold the
1962 entire decompressed kernel plus an additional 128 KiB.
1963 Platforms which normally make use of ROM-able zImage formats
1964 normally set this to a suitable value in their defconfig file.
1966 If ZBOOT_ROM is not enabled, this has no effect.
1969 bool "Compressed boot loader in ROM/flash"
1970 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1971 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1973 Say Y here if you intend to execute your compressed kernel image
1974 (zImage) directly from ROM or flash. If unsure, say N.
1977 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1978 depends on ZBOOT_ROM && ARCH_SH7372
1979 default ZBOOT_ROM_NONE
1981 Include experimental SD/MMC loading code in the ROM-able zImage.
1982 With this enabled it is possible to write the ROM-able zImage
1983 kernel image to an MMC or SD card and boot the kernel straight
1984 from the reset vector. At reset the processor Mask ROM will load
1985 the first part of the ROM-able zImage which in turn loads the
1986 rest the kernel image to RAM.
1988 config ZBOOT_ROM_NONE
1989 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1991 Do not load image from SD or MMC
1993 config ZBOOT_ROM_MMCIF
1994 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1996 Load image from MMCIF hardware block.
1998 config ZBOOT_ROM_SH_MOBILE_SDHI
1999 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2001 Load image from SDHI hardware block
2005 config ARM_APPENDED_DTB
2006 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2009 With this option, the boot code will look for a device tree binary
2010 (DTB) appended to zImage
2011 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2013 This is meant as a backward compatibility convenience for those
2014 systems with a bootloader that can't be upgraded to accommodate
2015 the documented boot protocol using a device tree.
2017 Beware that there is very little in terms of protection against
2018 this option being confused by leftover garbage in memory that might
2019 look like a DTB header after a reboot if no actual DTB is appended
2020 to zImage. Do not leave this option active in a production kernel
2021 if you don't intend to always append a DTB. Proper passing of the
2022 location into r2 of a bootloader provided DTB is always preferable
2025 config ARM_ATAG_DTB_COMPAT
2026 bool "Supplement the appended DTB with traditional ATAG information"
2027 depends on ARM_APPENDED_DTB
2029 Some old bootloaders can't be updated to a DTB capable one, yet
2030 they provide ATAGs with memory configuration, the ramdisk address,
2031 the kernel cmdline string, etc. Such information is dynamically
2032 provided by the bootloader and can't always be stored in a static
2033 DTB. To allow a device tree enabled kernel to be used with such
2034 bootloaders, this option allows zImage to extract the information
2035 from the ATAG list and store it at run time into the appended DTB.
2038 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2039 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2041 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2042 bool "Use bootloader kernel arguments if available"
2044 Uses the command-line options passed by the boot loader instead of
2045 the device tree bootargs property. If the boot loader doesn't provide
2046 any, the device tree bootargs property will be used.
2048 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2049 bool "Extend with bootloader kernel arguments"
2051 The command-line arguments provided by the boot loader will be
2052 appended to the the device tree bootargs property.
2057 string "Default kernel command string"
2060 On some architectures (EBSA110 and CATS), there is currently no way
2061 for the boot loader to pass arguments to the kernel. For these
2062 architectures, you should supply some command-line options at build
2063 time by entering them here. As a minimum, you should specify the
2064 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2067 prompt "Kernel command line type" if CMDLINE != ""
2068 default CMDLINE_FROM_BOOTLOADER
2071 config CMDLINE_FROM_BOOTLOADER
2072 bool "Use bootloader kernel arguments if available"
2074 Uses the command-line options passed by the boot loader. If
2075 the boot loader doesn't provide any, the default kernel command
2076 string provided in CMDLINE will be used.
2078 config CMDLINE_EXTEND
2079 bool "Extend bootloader kernel arguments"
2081 The command-line arguments provided by the boot loader will be
2082 appended to the default kernel command string.
2084 config CMDLINE_FORCE
2085 bool "Always use the default kernel command string"
2087 Always use the default kernel command string, even if the boot
2088 loader passes other arguments to the kernel.
2089 This is useful if you cannot or don't want to change the
2090 command-line options your boot loader passes to the kernel.
2094 bool "Kernel Execute-In-Place from ROM"
2095 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2097 Execute-In-Place allows the kernel to run from non-volatile storage
2098 directly addressable by the CPU, such as NOR flash. This saves RAM
2099 space since the text section of the kernel is not loaded from flash
2100 to RAM. Read-write sections, such as the data section and stack,
2101 are still copied to RAM. The XIP kernel is not compressed since
2102 it has to run directly from flash, so it will take more space to
2103 store it. The flash address used to link the kernel object files,
2104 and for storing it, is configuration dependent. Therefore, if you
2105 say Y here, you must know the proper physical address where to
2106 store the kernel image depending on your own flash memory usage.
2108 Also note that the make target becomes "make xipImage" rather than
2109 "make zImage" or "make Image". The final kernel binary to put in
2110 ROM memory will be arch/arm/boot/xipImage.
2114 config XIP_PHYS_ADDR
2115 hex "XIP Kernel Physical Location"
2116 depends on XIP_KERNEL
2117 default "0x00080000"
2119 This is the physical address in your flash memory the kernel will
2120 be linked for and stored to. This address is dependent on your
2124 bool "Kexec system call (EXPERIMENTAL)"
2125 depends on (!SMP || PM_SLEEP_SMP)
2127 kexec is a system call that implements the ability to shutdown your
2128 current kernel, and to start another kernel. It is like a reboot
2129 but it is independent of the system firmware. And like a reboot
2130 you can start any kernel with it, not just Linux.
2132 It is an ongoing process to be certain the hardware in a machine
2133 is properly shutdown, so do not be surprised if this code does not
2134 initially work for you.
2137 bool "Export atags in procfs"
2138 depends on ATAGS && KEXEC
2141 Should the atags used to boot the kernel be exported in an "atags"
2142 file in procfs. Useful with kexec.
2145 bool "Build kdump crash kernel (EXPERIMENTAL)"
2147 Generate crash dump after being started by kexec. This should
2148 be normally only set in special crash dump kernels which are
2149 loaded in the main kernel with kexec-tools into a specially
2150 reserved region and then later executed after a crash by
2151 kdump/kexec. The crash dump kernel must be compiled to a
2152 memory address not used by the main kernel
2154 For more details see Documentation/kdump/kdump.txt
2156 config AUTO_ZRELADDR
2157 bool "Auto calculation of the decompressed kernel image address"
2159 ZRELADDR is the physical address where the decompressed kernel
2160 image will be placed. If AUTO_ZRELADDR is selected, the address
2161 will be determined at run-time by masking the current IP with
2162 0xf8000000. This assumes the zImage being placed in the first 128MB
2163 from start of memory.
2167 menu "CPU Power Management"
2170 source "drivers/cpufreq/Kconfig"
2173 source "drivers/cpuidle/Kconfig"
2177 menu "Floating point emulation"
2179 comment "At least one emulation must be selected"
2182 bool "NWFPE math emulation"
2183 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2185 Say Y to include the NWFPE floating point emulator in the kernel.
2186 This is necessary to run most binaries. Linux does not currently
2187 support floating point hardware so you need to say Y here even if
2188 your machine has an FPA or floating point co-processor podule.
2190 You may say N here if you are going to load the Acorn FPEmulator
2191 early in the bootup.
2194 bool "Support extended precision"
2195 depends on FPE_NWFPE
2197 Say Y to include 80-bit support in the kernel floating-point
2198 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2199 Note that gcc does not generate 80-bit operations by default,
2200 so in most cases this option only enlarges the size of the
2201 floating point emulator without any good reason.
2203 You almost surely want to say N here.
2206 bool "FastFPE math emulation (EXPERIMENTAL)"
2207 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2209 Say Y here to include the FAST floating point emulator in the kernel.
2210 This is an experimental much faster emulator which now also has full
2211 precision for the mantissa. It does not support any exceptions.
2212 It is very simple, and approximately 3-6 times faster than NWFPE.
2214 It should be sufficient for most programs. It may be not suitable
2215 for scientific calculations, but you have to check this for yourself.
2216 If you do not feel you need a faster FP emulation you should better
2220 bool "VFP-format floating point maths"
2221 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2223 Say Y to include VFP support code in the kernel. This is needed
2224 if your hardware includes a VFP unit.
2226 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2227 release notes and additional status information.
2229 Say N if your target does not have VFP hardware.
2237 bool "Advanced SIMD (NEON) Extension support"
2238 depends on VFPv3 && CPU_V7
2240 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2243 config KERNEL_MODE_NEON
2244 bool "Support for NEON in kernel mode"
2245 depends on NEON && AEABI
2247 Say Y to include support for NEON in kernel mode.
2251 menu "Userspace binary formats"
2253 source "fs/Kconfig.binfmt"
2256 tristate "RISC OS personality"
2259 Say Y here to include the kernel code necessary if you want to run
2260 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2261 experimental; if this sounds frightening, say N and sleep in peace.
2262 You can also say M here to compile this support as a module (which
2263 will be called arthur).
2267 menu "Power management options"
2269 source "kernel/power/Kconfig"
2271 config ARCH_SUSPEND_POSSIBLE
2272 depends on !ARCH_S5PC100
2273 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2274 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2277 config ARM_CPU_SUSPEND
2282 source "net/Kconfig"
2284 source "drivers/Kconfig"
2288 source "arch/arm/Kconfig.debug"
2290 source "security/Kconfig"
2292 source "crypto/Kconfig"
2294 source "lib/Kconfig"
2296 source "arch/arm/kvm/Kconfig"